EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 304

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–14. DQS Update Enable Waveform
8–34
Stratix III Device Handbook, Volume 1
(Updated every 8 cycles)
DQS Delay Settings
Update Enable
Circuitry Output
System Clock
DLL Counter Update
(Every 8 cycles)
DQS Postamble Circuitry
For external memory interfaces that use a bi-directional read strobe like
DDR3, DDR2, and DDR SDRAM, the DQS signal is low before going to
or coming from a high-impedance state. The state where DQS is low, just
after a high-impedance state, is called the preamble and the state where
DQS is low, just before it returns to a high-impedance state, is called the
postamble. There are preamble and postamble specifications for both
read and write operations in DDR3, DDR2, and DDR SDRAM. The DQS
postamble circuitry, featured in
when there is noise on the DQS line at the end of a read postamble time.
Stratix III devices have a dedicated postamble register that can be
controlled to ground the shifted DQS signal used to clock the DQ input
registers at the end of a read operation. This ensures that any glitches on
the DQS input signals at the end of the read postamble time do not affect
the DQ IOE registers.
6 bit
Figure
8–15, ensures that data is not lost
DLL Counter Update
(Every 8 cycles)
Altera Corporation
November 2007