EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 138

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Operational Mode Descriptions
Figure 5–20. Round and Saturation Locations
5–38
Stratix III Device Handbook, Volume 1
16 User defined SAT Positions (bit 43-28)
43
43
42
42
In 2’s complement format, the maximum negative number that can be
represented is –2
Symmetrical saturation will limit the maximum negative number to
–2
■
■
Table 5–8
is saturated to 36-bits.
Stratix III devices have up to 16 configurable bit positions out of the 44-bit
bus ([43:0]) for the round and saturate logic unit providing higher
flexibility. You must select the 16 configurable bit positions at compile
time. These 16-bit positions are located at bits [21:6] for rounding and
[43:28] for saturation, as shown in
1
44 to 36 Bits Saturation Symmetric SAT Result
Table 5–8. Examples of Saturation
(n–1)
29
Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000
Symmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000001
5926AC01342h
ADA38D2210h
+ 1. For example, for 32 bits:
28
For symmetric saturation, the RND bit position is also used to
determine where the LSP for the saturated data is located.
shows how the saturation works. In this example, a 44-bit input
16 User defined RND Positions (bit 21-6)
(n–1)
21
while the maximum positive number is 2
20
7FFFFFFFFh
800000001h
Figure
5–20.
7
Asymmetric SAT Result
6
7FFFFFFFFh
800000000h
Altera Corporation
October 2007
(n–1)
1
–1.
0
0