EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 318

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Banks
I/O Banks
Figure 9–1. I/O Banks in Stratix III
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
9–2
Stratix III Device Handbook, Volume 1
PLL_L2
PLL_L1
PLL_L3
PLL_L4
Stratix III I/O Banks
Figure 9–1
representation only. Refer to the pin list and Quartus II software for exact locations.
Differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted
to support differential I/O operations.
Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without on-chip differential
OCT support.
Column I/O supports LVDS outputs using SE buffers and external resistor networks.
Row I/O supports PCI/PCI-X without on-chip clamping diodes.
The PLL blocks are shown for location purposes only and are not considered additional banks. The PLL input and
output uses the I/Os in adjacent banks.
Figure
Bank 8A
Bank 3A
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation
is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
9–1:
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation
Bank 3B
Bank 8B
The Stratix III I/Os are divided into 16 to 24 I/O banks. The dedicated
circuitry that supports high-speed differential I/Os is located in banks in
the right side and left side of the device.
banks and the I/O standards supported by the banks.
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15 Class II,
differential HSTL-12 Class II standards are only supported
for input operations
Bank 3C
Bank 8C
Notes
(2), (3), (4), (5),
PLL_B1 PLL_B2
PLL_T1
PLL_T2
(6)
Bank 4C
Bank 7C
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation
Figure 9–1
Bank 4B
Bank 7B
shows the different
Bank 4A
Bank 7A
Altera Corporation
November 2007
PLL_R2
PLL_R3
PLL_R4
PLL_R1