EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 706

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
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I/O Timing
1–194
Stratix III Device Handbook, Volume 2
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVCMOS
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVTTL
3.0-V LVTTL
3.0-V LVCMOS
3.0-V LVCMOS
Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part 1 of 5)
I/O Standard
Strength
Current
12mA
12mA
4mA
8mA
4mA
8mA
4mA
8mA
4mA
8mA
Table 1–88
single-ended I/O standards.
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Parameter
specifies EP3SL200 Row Pins Output Timing parameters for
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
Industrial Commercial
Fast Model
3.941
2.301
3.814
2.174
4.061
2.421
3.972
2.332
3.971
2.331
3.941
2.301
3.814
2.174
4.061
2.421
3.972
2.332
3.971
2.331
5.822 6.692 6.802 6.645 7.171
3.236 3.808 3.676 3.832 3.831
5.628 6.416 6.576 6.419 6.895
3.042 3.532 3.450 3.556 3.555
5.999 6.838 7.006 6.849 7.317
3.413 3.954 3.880 3.978 3.977
5.877 6.707 6.865 6.708 7.186
3.291 3.823 3.739 3.847 3.846
5.850 6.661 6.834 6.677 7.140
3.264 3.777 3.708 3.801 3.800
5.822 6.692 6.802 6.645 7.171
3.236 3.808 3.676 3.832 3.831
5.628 6.416 6.576 6.419 6.895
3.042 3.532 3.450 3.556 3.555
5.999 6.838 7.006 6.849 7.317
3.413 3.954 3.880 3.978 3.977
5.877 6.707 6.865 6.708 7.186
3.291 3.823 3.739 3.847 3.846
5.850 6.661 6.834 6.677 7.140
3.264 3.777 3.708 3.801 3.800
V
1.1V
CCL
-2
=
V
1.1V
CCL
-3
Altera Corporation
=
November 2007
V
1.1V
CCL
-4
=
V
1.1V
CCL
=
-4L
V
0.9V
CCL
=
Units
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ns
ns
ns
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