EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 255

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–20. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
Notes to
(1)
(2)
(3)
Termination
Schemes for I/O
Standards
Altera Corporation
November 2007
S2PENA_1A (2)
S2PENA_2A (3)
OCTUSRCLK
ts2p ≥ 25ns
S2PENA_1A is asserted in Bank 1A for calibration block 0.
S2PENA_2A is asserted in Bank 2A for calibration block 1.
ENASER0
ENASER1
nCLRUSR
ENAOCT
Figure
7–20:
R
If only R
corresponding ENASER signal only needs to be asserted for 240
OCTUSRCLK cycles for calibration.
1
The following section describes the different termination schemes for the
I/O standards used in Stratix III devices.
Single-Ended I/O Standards Termination
Voltage-referenced I/O standards require both an input reference
voltage, V
receiving device tracks the termination voltage of the transmitting device
Figures 7–21
termination on Stratix III devices.
1000
S
CY CLE S
Calibration
OCTUSRCLK
Calibration Phase
S
You still have to assert the ENASER signal for 28 OCTUSRCLK
cycles for serial transfer.
calibration is used for an OCT calibration block, its
REF
1000
, and a termination voltage, V
and
CY CLE S
OCTUSRCLK
7–22
show the details of SSTL and HSTL I/O
28
OCTUSRCLK
CY CLE S
Stratix III Device Handbook, Volume 1
TT
. The reference voltage of the
Stratix III Device I/O Features
ts2p (1)
28
OCTUSRCLK
CY CLE S
ts2p (1)
7–37