EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 245

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
On-Chip Parallel Termination with Calibration
Stratix III devices support on-chip parallel termination with calibration in
all banks. On-chip parallel termination with calibration is only supported
for input or bi-directional pin configurations. Output pin configurations
do not support on-chip parallel termination with calibration.
shows on-chip parallel termination with calibration.
Figure 7–11. Stratix III On-Chip Parallel Termination with Calibration
The on-chip parallel termination calibration circuit compares the total
impedance of the I/O buffer to the external 50-Ω ±1% resistors connected
to the R
until they match. Calibration occurs at the end of the device
configuration. When the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
Table 7–7
termination with calibration.
SSTL-2 Class I, II
SSTL-18 Class I, II
SSTL-15 Class I, II
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
Differential SSTL-2
Class I, II
Table 7–7. Selectable I/O Standards with On-Chip Parallel Termination with
Calibration (Part 1 of 2)
I/O Standard
UP
Transmitter
and R
shows the list of I/O standards that support on-chip parallel
DN
pins and dynamically enables or disables the transistors
Termination Setting
On-Chip Parallel
(Column I/O)
50
50
50
50
50
50
50
Z
O
= 50 Ω
Stratix III Device Handbook, Volume 1
V
REF
Termination Setting
On-Chip Parallel
Stratix III Device I/O Features
(Row I/O)
V
GND
50
50
50
50
50
50
50
CCIO
100 Ω
100 Ω
Receiver
Stratix III OCT
Figure 7–11
Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
7–27