EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 327

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 9–9. Soft-CDR Data and Clock Path
Altera Corporation
November 2007
core
Data to Core
10
Deserializer
CLK_BS_DES
An independent reset port, RX_RESET, is available to reset the DPA
circuitry. The DPA circuitry must be retrained after reset.
Soft-CDR Mode
The Stratix III LVDS channel offers the soft-CDR mode to support the
Gigabit Ethernet/SGMII protocols. Clock-data recovery (CDR) is
required to extract the clock out of the clock-embedded data to support
SGMII. In Stratix III devices, the CDR circuit is implemented in soft-logic
as an IP.
In soft-CDR mode, the DPA circuitry selects an optimal DPA clock phase
to sample the data and carry on the bit slip operation and deserialization.
The selected DPA clock is also divided down by the deserialization factor,
and then forwarded to the PLD core along with the deserialized data. The
LVDS block has an output called DIVCLKOUT for the forwarded clock
signal. This signal is put on the newly introduced PCLK (Periphery
Clock) network. In Stratix III, every LVDS channel can be used in
soft-CDR mode and can drive the core via the PCLK network.
shows the path enabled in soft-CDR mode.
1
DPA CLK
PCLK
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Note that the synchronizer FIFO is bypassed in soft-CDR mode.
The reference clock frequency must be suitable for the PLL to
generate a clock that matches the data rate of the interface. The
DPA circuitry can track PPM differences between the reference
clock and the data stream.
Bit Slip
Clock Forwarding
Divide Down
ReTimed
Data
and
DPA
Stratix III Device Handbook, Volume 1
LVDS Data
CLOCK
TREE
DPA
PLL
Figure 9–9
9–11
Clock
Ref