EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 442

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1 Boundary-Scan Register
Figure 13–2. IEEE Std. 1149.1 Circuitry
Note to
(1)
IEEE Std. 1149.1
Boundary-Scan
Register
13–4
Stratix III Device Handbook, Volume 1
TCLK
TRST
TMS
For register lengths, see the device data sheet in the Configuring Stratix III Devices chapter in volume 1 of the
Stratix III Device Handbook.
TDI
Figure
13–2:
Controller
TAP
UPDATEIR
UPDATEDR
CLOCKIR
CLOCKDR
SHIFTIR
SHIFTDR
IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port
(TAP) controller. For more information on the TAP controller, refer to
“IEEE Std. 1149.1 BST Operation Control” on page
pins operate the TAP controller. The TDI and TDO pins provide the serial
path for the data registers. The TDI pin also provides data to the
instruction register, which then generates control logic for the data
registers.
The boundary-scan register is a large serial shift register that uses the TDI
pin as an input and the TDO pin as an output. The boundary-scan register
consists of three-bit peripheral elements that are associated with
Stratix III I/O pins. You can use the boundary-scan register to test
external pin connections or to capture internal data.
Data Registers
Instruction Register
Bypass Register
Boundary-Scan Register
Device ID Register
ICR Registers
Instruction Decode
a
(1)
(1)
13–9. The TMS and TCK
Altera Corporation
November 2007
TDO