EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 24

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Architecture Features
1–6
Stratix III Device Handbook, Volume 1
f
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functions. The Quartus II Compiler places associated logic in an LAB or
adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
The Logic Array Block (LAB) of Stratix-III has a new derivative called
Memory LAB (or MLAB), which adds SRAM memory capability to the
LAB. MLAB is a superset of the LAB and includes all LAB features.
MLABs support a maximum of 640-bits of simple dual-port Static
Random Access Memory (SRAM). Each ALM in an MLAB can be
configured as either a 64×1 or 32×2 block, resulting in a configuration
of 64×10 or 32×20 simple dual port SRAM block. MLAB and LAB blocks
always co-exist as pairs in all Stratix-III families allowing up to 50% of the
logic (LABs) to be traded for memory (MLABs).
For more information on LABs and ALMs, refer to the
and Adaptive Logic Modules in Stratix III Devices
Stratix III Device Handbook.
For more information on MLAB modes, features and design
considerations, refer to the
Stratix III Devices
MultiTrack Interconnect
In the Stratix III architecture, connections between ALMs, TriMatrix
memory, DSP blocks, and device I/O pins are provided by the
MultiTrack interconnect structure with DirectDrive technology. The
MultiTrack interconnect consists of continuous, performance-optimized
row and column interconnects that span fixed distances. A routing
structure with fixed length resources for all devices allows predictable
and repeatable performance when migrating through different device
densities. The MultiTrack interconnect provides 1-hop connection to 34
adjacent LABs, 2-hop connections to 96 adjacent LABs and 3 hop
connections to 160 adjacent LABs.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
reoptimization cycles that typically follow design changes and additions.
The Quartus II Compiler also automatically places critical design paths
on faster interconnects to improve design performance.
For more information, refer to the
Devices
chapter in volume 1 of the Stratix III Device Handbook.
chapter in volume 1 of the Stratix III Device Handbook.
TriMatrix Embedded Memory Blocks in
MultiTrack Interconnect in Stratix III
chapter in volume 1 of the
Logic Array Blocks
Altera Corporation
November 2007