EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 338

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential Pin Placement Guidelines
9–22
Stratix III Device Handbook, Volume 1
Figure 9–18. Single-Ended Output Pin Placement with Respect to the
Differential I/O Pin
DPA-Enabled Channel Driving Distance
■
■
■
Each left/right PLL (in DPA mode) can drive up to 26 contiguous
LAB rows. The 26-row limit includes any channels that are skipped
during pin placement and any channels that are not bonded out to
the pins. See
Center left/right PLLs (in DPA mode) can drive up to 52 LAB rows
(26 contiguous rows on the upper banks and 26 contiguous rows on
the lower banks simultaneously, as shown in
The 26 contiguous rows do not need to be adjacent to the
driving PLL.
Figure 9–19
for more details.
Single-Ended Outputs
Not Allowed
Row Boundary
Single-Ended Output Pin
Differential I/O Pin
Single-Ended Input Pin
Figure
Altera Corporation
9–19).
November 2007