EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 152

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
6–2
Stratix III Device Handbook, Volume 1
Stratix III devices have up to 32 dedicated single-ended clock pins or
16 dedicated differential clock pins (CLK[0:15]p and CLK[0:15]n)
that can drive either the GCLK or RCLK networks. These clock pins are
arranged on the four sides of the Stratix III device, as shown in
Figures 6–1
Global Clock Networks
Stratix III devices provide up to 16 GCLKs that can drive throughout the
entire device, serving as low-skew clock sources for functional blocks like
adaptive logic modules (ALMs), digital signal processing (DSP) blocks,
TriMatrix memory blocks, and PLLs. Stratix III device I/O elements
Notes to
(1)
(2)
(3)
(4)
Clock input pins
Global clock networks 16
Regional clock
networks
Peripheral clock
networks
GCLKs/RCLKs per
quadrant
GCLKs/RCLKs per
device
Table 6–1. Clock Resources in Stratix III Devices
Clock Resource
There are 64 RCLKs in EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50,
EP3SE80, and EP3SE110 devices. There are 88 RCLKs in EP3SL200, EP3SE260,
and EP3SL340 devices.
There are a total of 56 PCLKs in EP3SL50, EP3SL70, and EP3SE50 devices. There
are 88 PCLKs in EP3SL110, EP3SL150, EP3SL200, EP3SE80, and EP3SE110
devices. There are 112 PCLKs in EP3SE260 and 116 PCLKs in the EP3SL340
device.
There are 32 GCLKs/RCLKs per quadrant in EP3SL50, EP3SL70, EP3SL110,
EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices. There are 38
GCLKs/RCLKs per quadrant in EP3SL200, EP3SE260, and EP3SL340 devices.
There are 80 GCLKs/RCLKs per entire device in EP3SL50, EP3SL70, EP3SL110,
EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices. There are 104
GCLKs/RCLKS per entire device in EP3SL200, EP3SE260, and EP3SL340
devices.
Table
to 6–4.
6–1:
32 Single-ended
(16 Differential)
64/88
116 (29 per device
quadrant)
32/38
80/104
# of Resources
Available
(1)
(3)
(4)
(2)
CLK[0..15]p
CLK[0..15]n
CLK[0..15]p/n
clock outputs, and logic array
CLK[0..15]p/n
clock outputs, and logic array
DPA clock outputs, horizontal
I/O pins, and logic array
16 GCLKs + 16 RCLKs/
16 GCLKs + 22 RCLKs
16 GCLKs + 64 RCLKs /
16 GCLKs + 88 RCLKs
Source of Clock Resource
Altera Corporation
and
pins
November 2007
pins, PLL
pins, PLL