ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 74

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
Table 13-2
ure 13-5
in the modules having the alternate function.
Table 13-2.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
are not shown in the succeeding tables. The overriding signals are generated internally
summarizes the function of the overriding signals. The pin and port indexes from
Full Name
Pull-up Override
Enable
Pull-up Override Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value Override
Enable
Port Value Override
Value
Digital Input Enable
Override Enable
Digital Input Enable
Override Value
Digital Input
Analog Input/output
Generic Description of Overriding Signals for Alternate Functions
Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when {DDxn,
PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn, and
PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is enabled
by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when DDOV
is set/cleared, regardless of the setting of the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the port value
is controlled by the PVOV signal. If PVOE is cleared, and the
Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the DIEOV
signal. If this signal is cleared, the Digital Input Enable is
determined by MCU state (Normal mode, sleep modes).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV
is set/cleared, regardless of the MCU state (Normal mode, sleep
modes).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but before
the synchronizer. Unless the Digital Input is used as a clock
source, the module with the alternate function will use its own
synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
ATmega64A
Fig-
74