ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 56

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3
10.3.1
10.3.2
8160C–AVR–07/09
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 0
Safety Level 1
Table 10-1.
Figure 10-7. Watchdog Timer
The sequence for changing configuration differs slightly between the three safety levels. Sepa-
rate procedures are described for each level.
This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog
Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
The Time-out period can be changed at any time without restriction. To disable an enabled
Watchdog Timer, the procedure described on
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out
period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or
changing the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as
M103C
Unprogrammed
Unprogrammed
Programmed
Programmed
to WDE regardless of the previous value of the WDE bit.
desired, but with the WDCE bit cleared.
WDT Configuration as a Function of the Fuse Settings of M103C and WDTON
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
OSCILLATOR
WATCHDOG
Safety
Level
1
2
0
2
page 57
WDT Initial
State
Disabled
Enabled
Disabled
Enabled
(WDE bit description) must be followed.
How to Disable
the WDT
Timed
sequence
Always enabled
Timed
sequence
Always enabled
ATmega64A
How to Change
Time-out
Timed sequence
Timed sequence
No restriction
Timed sequence
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