ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 21

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3
7.3.1
7.3.2
8160C–AVR–07/09
EEPROM Data Memory
EEPROM Read/Write Access
EEPROM Write During Power-down Sleep Mode
Figure 7-3.
The ATmega64A contains 2K bytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programming” on page 295
in SPI, JTAG, or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
however, lets the user software detect when the next byte can be written. If the user code con-
tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock frequency
used.
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
When entering Power-down Sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the oscillator continues running, and
See “Preventing EEPROM Corruption” on page 22.
Address
clk
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for
Compute Address
T1
Memory Access Instruction
contains a detailed description on EEPROM programming
Address Valid
Table 7-5 on page
T2
for details on how to avoid problems in
Next Instruction
T3
34. A self-timing function,
ATmega64A
21