ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 164

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. SPI – Serial Peripheral Interface
19.1
19.2
8160C–AVR–07/09
Features
Overview
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Figure 19-1. SPI Block Diagram
Note:
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega64A and peripheral devices or between several AVR devices. The interconnection
between Master and Slave CPUs with SPI is shown in
Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle
when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the
data to be sent in their respective Shift Registers, and the Master generates the required clock
pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
(1)
2, and
Table 13-6 on page 76
Figure
19-2. The system consists of two
for SPI pin placement.
ATmega64A
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