ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 110
ATMEGA64A-MNR
Manufacturer Part Number
ATMEGA64A-MNR
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64A-AU.pdf
(392 pages)
Specifications of ATMEGA64A-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA64A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.11.7
8160C–AVR–07/09
SFIOR – Special Function IO Register
the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00.
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to PSR0 and PSR321 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit written zero, the PSR0 and PSR321 bits are cleared by hardware, and
the Timer/Counters start counting simultaneously.
• Bit 1 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be reset. The bit is normally cleared
immediately by hardware. If this bit is written when Timer/Counter0 is operating in Asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set.
Bit
0x20 (0x40)
Read/Write
Initial Value
TSM
R/W
7
0
R
6
–
0
R
5
–
0
R
4
–
0
ACME
R/W
3
0
PUD
R/W
2
0
PSR0
R/W
ATmega64A
1
0
PSR321
R/W
0
0
SFIOR
110
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