ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 196

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.11 Register Description
20.11.1
20.11.2
8160C–AVR–07/09
UDRn – USART I/O Data Register
UCSRnA – USART Control and Status Register A
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXBn) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn flag is not set, will be ignored by the USART transmitter.
When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will
load the data into the Transmit Shift Register when the Shift Register is empty. Then the data
will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify
write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC
and SBIS), since these also will change the state of the FIFO.
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDR). The TXC flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXC flag can generate a Transmit Complete interrupt (see descrip-
tion of the TXCIE bit).
• Bit 5 – UDREn: USART Data Register Empty
The UDREn flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDREn is
one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data
Register Empty interrupt (see description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCn
R/W
7
0
R
7
0
R/W
TXCn
R/W
6
0
6
0
R/W
UDREn
5
0
R
5
1
R/W
4
0
FEn
RXB[7:0]
R
TXB[7:0]
4
0
R/W
3
0
DORn
R
3
0
R/W
2
0
UPEn
R
2
0
R/W
1
0
U2Xn
R/W
1
0
ATmega64A
R/W
0
0
MPCMn
R/W
0
0
UDnR (Read)
UDnR (Write)
UCSRnA
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