ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 217

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21-3.
8160C–AVR–07/09
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x38
0x40
0x48
0x50
0x58
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
Status Codes for Master Receiver Mode
enables the master to switch between slaves, Master Transmitter mode and Master Receiver
mode without losing control over the bus.
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
Application Software Response
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWEA
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
Two-wire Serial Bus will be released and not ad-
dressed Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO flag will be reset
ATmega64A
217