ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 333

IC MCU AVR 64K FLASH 8QFN

ATMEGA64A-MNR

Manufacturer Part Number
ATMEGA64A-MNR
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64A-MNR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA64A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
28.7
8160C–AVR–07/09
SPI Timing Characteristics
See
Table 28-5.
Note:
Figure 28-4. SPI Interface Timing Requirements (Master Mode)
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 28-4 on page 333
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
Description
1. In SPI Programming mode the minimum SCK high/low period is:
SS high to tri-state
SCK to out high
SCK to SS high
- 2 t
- 3 t
SCK high/low
MISO
MOSI
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SCK
SCK
SS low to out
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
SS
SPI Timing Parameters
CLCL
CLCL
Setup
Setup
Hold
Hold
for f
for f
CK
CK
(1)
< 12 MHz
>12 MHz
6
4
MSB
5
MSB
and
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Figure 28-5 on page 334
7
4 • t
2 • t
Min
10
20
20
t
ck
...
ck
ck
...
See
50% duty cycle
0.5 • t
Table 19-5
for details.
Typ
3.6
10
10
10
10
15
15
10
2
sck
LSB
1
LSB
ATmega64A
2
Max
1.6
3
8
ns
µs
ns
333

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