ATMEGA64-16MJ Atmel, ATMEGA64-16MJ Datasheet

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ATMEGA64-16MJ

Manufacturer Part Number
ATMEGA64-16MJ
Description
IC MCU AVR 64K 5V 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64-16MJ

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 64 Kbytes of In-System Reprogrammable Flash program memory
– 2 Kbytes EEPROM
– 4 Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64 Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7V - 5.5V for ATmega64L
– 4.5V - 5.5V for ATmega64
– 0 - 8 MHz for ATmega64L
– 0 - 16 MHz for ATmega64
True Read-While-Write Operation
Capture Mode
and Extended Standby
In-System Programming by On-chip Boot Program
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain (1x, 10x, 200x)
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
ATmega64
ATmega64L
Summary
2490QS–AVR–07/10

Related parts for ATMEGA64-16MJ

ATMEGA64-16MJ Summary of contents

Page 1

... Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for ATmega64L – 4.5V - 5.5V for ATmega64 • Speed Grades – MHz for ATmega64L – MHz for ATmega64 ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 64K Bytes ...

Page 2

... Pin Configuration Figure 1. Pinout ATmega64 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology ...

Page 3

... Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...

Page 4

... ATmega103, all I/O locations present in ATmega103 have the same location in Compatibility ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (that is, in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64 as listed on 74. 2490QS–AVR–07/10 ...

Page 6

... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64 as listed on 81. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter ...

Page 7

... This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation. 2490QS–AVR–07/10 , even if the ADC is not used. If the ADC is used, it should be connected ATmega64(L) Table 19 on page CC 7 ...

Page 8

... A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega64( 2490QS–AVR–07/10 ...

Page 9

... PORTG4 PORTG3 – – DDG4 DDG3 – – PING4 PING3 PORTF6 PORTF5 PORTF4 PORTF3 DDF6 DDF5 DDF4 DDF3 ATmega64(L) Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – UCSZ11 UCSZ10 UCPOL1 UPE1 U2X1 ...

Page 10

... ADMUX REFS1 0x06 (0x26) ADCSRA ADEN 0x05 (0x25) ADCH 0x04 (0x24) ADCL 0x03 (0x23) PORTE PORTE7 0x02 (0x22) DDRE DDE7 0x01 (0x21) PINE PINE7 ATmega64(L) 10 Bit 6 Bit 5 Bit 4 Bit 3 – – – – SP14 SP13 SP12 SP11 SP6 SP5 ...

Page 11

... I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 2490QS–AVR–07/10 Bit 6 Bit 5 Bit 4 Bit 3 PINF6 PINF5 PINF4 PINF3 ATmega64(L) Bit 2 Bit 1 Bit 0 PINF2 PINF1 PINF0 Page 89 11 ...

Page 12

... Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared ATmega64(L) 12 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 13

... Set Twos Complement Overflow. CLV Clear Twos Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG 2490QS–AVR–07/10 ATmega64( then PC ← None then PC ← None Rd ← Rr None Rd+1:Rd ← Rr+1:Rr None Rd ← K None Rd ← ...

Page 14

... Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega64( ← None (see specific descr. for Sleep function) None (see specific descr. for WDR/timer) None For On-chip Debug Only None 1 ...

Page 15

... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2490QS–AVR–07/10 (2) (1) Ordering Code Package ATmega64L-8AU 64A ATmega64L-8MU 64M1 ATmega64-16AU 64A ATmega64-16MU 64M1 Package Type ATmega64(L) Operation Range Industrial ° ° (- ...

Page 16

... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega64( PIN 1 IDENTIFIER ...

Page 17

... Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega64(L) C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A 0 ...

Page 18

... Errata The revision letter in this section refers to the revision of the ATmega64 device. ATmega64, rev. A • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • ...

Page 19

... Always use OUT or SBI to set EERE in EECR. 2490QS–AVR–07/10 If ATmega64 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega64 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 20

... Added note to 2490K-04/ Updated Rev. 2490L-10/06 3. Updated on page 4. Updated ATmega64(L) 20 Table 117, “Extended Fuse Byte,” on page “Performing Page Erase by SPM” on page Table 133, “Two-wire Serial Bus Requirements,” on page 328 “Errata” on page 379. “DC Characteristics” on page 325 “ ...

Page 21

... Table 134 on page 330. “Analog to Digital Converter” on page “Electrical Characteristics” on page “ATmega103 and ATmega64 Compatibility” on page “External Memory Interface” on page 27 “WDTCR – Watchdog Timer Control Register” on page “Unconnected Pins” on page Table 19 on page 52, Table 20 on page 135 ...

Page 22

... Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03 ATmega64(L) 22 12. Updated features in“Analog to Digital Converter” on page 230 on page 333. 13. Updated “Ordering Information” on page 1. Updated “Errata” on page 18. ...

Page 23

... Table 136 on page 242. and Figure 147 on page 306 a note regarding usage “TWI – Two-wire Serial Interface” on page 204. Added the description at the end of 205. ATmega64(L) 52. 308. 16. “Ordering Information” on page 39. 38, Table 9 on page 41, Table 10 on page Table 16 on page ...

Page 24

In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “OSCCAL – Oscillator Calibration Register(1)” ...

Page 25

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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