ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 199

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn flag in UCSRnB will be set.
Table 20-9.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 20-10. USBS Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character Size) in a frame the Receiver and Transmitter use.
Table 20-11. UCSZ Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 20-12. UCPOL Bit Settings
UCPOLn
UCSZn2
0
1
UPMn1
0
0
0
0
1
1
1
1
0
0
1
1
UPM Bits Settings
USBSn
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
0
1
UCSZn1
UPMn0
0
0
1
1
0
0
1
1
0
1
0
1
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
UCSZn0
0
1
0
1
0
1
0
1
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
Stop Bit(s)
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
1-bit
2-bit
ATmega64A
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