ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 32

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6.3
7.6.4
8160C–AVR–07/09
XMCRB – External Memory Control Register B
EEARH and EEARL – EEPROM Address Register
• Bit 7 – XMBK: External Memory Bus Keeper Enable
Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is
enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise
be tri-stated. Writing XMBK to zero disables the Bus Keeper. XMBK is not qualified with SRE, so
even if the XMEM interface is disabled, the Bus Keepers are still activated as long as XMBK is
one.
• Bit 6:3 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60KB address space is not required to access the external memory, some, or all, Port
C pins can be released for normal port pin function as described in
“Using all Locations of External Memory Smaller than 64 KB” on page
the XMMn bits to access all 64KB locations of the external memory.
Table 7-4.
Bit
(0x6C)
Read/Write
Initial Value
Bit
0x1F (0x3F)
0x1E (0x3E)
Read/Write
Initial Value
XMM2
0
0
0
0
1
1
1
1
XMM1
0
0
1
1
0
0
1
1
EEAR7
XMBK
Port C Pins Released as Normal Port Pins when the External Memory is Enabled
R/W
R/W
15
R
X
7
0
–
7
0
XMM0
EEAR6
0
1
0
1
0
1
0
1
R/W
14
R
X
R
–
6
0
6
–
0
# Bits for External Memory Address
8 (Full 60 KB space)
7
6
5
4
3
2
No Address high bits
EEAR5
R/W
13
R
X
–
5
0
R
5
–
0
EEAR4
R/W
12
R
–
4
0
X
R
4
–
0
EEAR3
R/W
11
R
–
3
0
X
R
3
–
0
EEAR10
EEAR2
XMM2
R/W
R/W
R/W
10
X
X
2
2
0
EEAR9
EEAR1
Table
XMM1
R/W
R/W
R/W
X
X
1
0
9
1
27, it is possible to use
ATmega64A
Released Port Pins
None
PC7
PC7 - PC6
PC7 - PC5
PC7 - PC4
PC7 - PC3
PC7 - PC2
Full Port C
7-4. As described in
EEAR8
EEAR0
XMM0
R/W
R/W
R/W
X
X
8
0
0
0
XMCRB
EEARH
EEARL
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