ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 181

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.6
20.6.1
8160C–AVR–07/09
Data Transmission – The USART Transmitter
Sending Frames with 5 to 8 Data Bits
More advanced initialization routines can be made that include frame format as parameters, dis-
able interrupts and so on. However, many applications use a fixed setting of the baud and
control registers, and for these types of applications the initialization code can be placed directly
in the main routine, or be combined with initialization code for other I/O modules.
The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB
Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid-
den by the USART and given the function as the transmitter’s serial output. The baud rate, mode
of operation and frame format must be set up once before doing any transmissions. If synchro-
nous operation is used, the clock on the XCK pin will be overridden and used as transmission
clock.
A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The
CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or
immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the baud register,
U2Xn bit or by XCK depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDREn) flag. When using frames with less than eight bits, the most signif-
icant bits written to the UDRn are ignored. The USART has to be initialized before the function
can be used. For the assembly code, the data to be sent is assumed to be stored in register R16
Note:
Assembly Code Example
C Code Example
USART_Transmit:
void USART_Transmit( unsigned char data )
{
}
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out
ret
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn)) )
/* Put data into buffer, sends the data */
UDRn = data;
1. See “About Code Examples” on page 8.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
UDRn,r16
;
(1)
(1)
ATmega64A
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