ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 158

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
Normal or CTC mode (non-PWM).
Table 17-3.
Mode
0
1
2
3
COM21
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
151.
Table 17-3
WGM21
However, the functionality and location of these bits are compatible with previous versions of
the timer.
(CTC2)
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, non-PWM Mode
COM20
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
WGM20
(PWM2)
0
1
0
1
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on Compare Match.
Clear OC2 on Compare Match.
Set OC2 on Compare Match.
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
Table 17-2
(1)
TOP
0xFF
0xFF
OCR2
0xFF
Update of
OCR2
TOP
Immediate
Immediate
BOTTOM
and
ATmega64A
“Modes of Operation”
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
158