ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 49

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.7.4
9.7.5
9.7.6
9.7.7
8160C–AVR–07/09
Internal Voltage Reference
Watchdog Timer
Port Pins
JTAG Interface and On-chip Debug System
hence, always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to
configure the Brown-out Detector.
The internal voltage reference will be enabled when needed by the Brown-out Detector, the Ana-
log Comparator or the ADC. If these modules are disabled as described in the sections above,
the internal voltage reference will be disabled and it will not be consuming power. When turned
on again, the user must allow the reference to start up before the output is used. If the reference
is kept on in sleep mode, the output can be used immediately. Refer to
ence” on page 55
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the both the I/O clock (clk
device will be disabled. This ensures that no power is consumed by the input logic when not
needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will
then be enabled. Refer to the section
details on which pins are enabled. If the input buffer is enabled and the input signal is left floating
or have an analog signal level close to V
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or
Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will
contribute significantly to the total current consumption. There are three alternative ways to
avoid this:
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is
not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,
power consumption will increase. Note that the TDI pin for the next device in the scan chain con-
tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or
leaving the JTAG fuse unprogrammed disables the JTAG interface.
• Disable OCDEN Fuse.
• Disable JTAGEN Fuse.
• Write one to the JTD bit in MCUCSR.
“Watchdog Timer” on page 55
for details on the start-up time.
I/O
) and the ADC clock (clk
“Digital Input Enable and Sleep Modes” on page 72
“Brown-out Detector” on page 48
CC
/2, the input buffer will use excessive power.
for details on how to configure the Watchdog Timer.
ADC
) are stopped, the input buffers of the
“Internal Voltage Refer-
ATmega64A
for details on how to
for
49