ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 31

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
Table 7-2.
• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait states for the upper sector of the exter-
nal memory address space, see
• Bit 3:2 – SRW01, SRW00: Wait State Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait states for the lower sector of the exter-
nal memory address space, see
Table 7-3.
Note:
• Bit 0 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
SRWn1
SRL2
0
0
1
1
0
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait states of the External Memory Interface, see
6
SRWn0
to
Sector Limits with Different Settings of SRL2:0
Wait States
Figure 7-9
0
1
0
1
SRL1
0
0
1
1
0
0
1
1
Wait States
No wait states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out new
address
how the setting of the SRW bits affects the timing.
(1)
SRL0
Table
Table
0
1
0
1
0
1
0
1
7-3.
7-3.
Sector Limits
Lower sector = N/A
Upper sector = 0x1100 - 0xFFFF
Lower sector = 0x1100 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
Lower sector = 0x1100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x1100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x1100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x1100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x1100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x1100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
ATmega64A
Figure 7-
31