ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 17

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. AVR Memories
7.1
8160C–AVR–07/09
In-System Reprogrammable Flash Program Memory
This section describes the different memories in the ATmega64A. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega64A features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
The ATmega64A contains 64K bytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
32K x 16. For software security, the Flash Program memory space is divided into two sections,
Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega64A
Program Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The
operation of Boot Program section and associated Boot Lock bits for software protection are
described in detail in
“Memory Programming” on page 295
SPI, JTAG, or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
13.
“Boot Loader Support – Read-While-Write Self-programming” on page
contains a detailed description on Flash programming in
“Instruction Execution Tim-
ATmega64A
281.
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