ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 189

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.8.3
8160C–AVR–07/09
Asynchronous Operational Range
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error n (FEn) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see
Table
bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
Table 20-2
that Normal Speed mode has higher toleration of baud rate variations.
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
20-2) base frequency, the Receiver will not be able to synchronize the frames to the start
R
slow
and
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
accepted in relation to the receiver baud rate.
=
Table 20-3
M
= 5 for Double Speed mode.
------------------------------------------ -
S 1
–
Figure
(
1
1
D
+
+
D S ⋅
2
1
list the maximum Receiver baud rate error that can be tolerated. Note
20-7. For Double Speed mode the first low level must be delayed to
)S
3
2
+
S
4
F
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
R
10
fast
(A)
0/1
6
=
F
0/1
-----------------------------------
(
= 8 for Normal Speed and S
D
M
(
(B)
0/1
0/1
+
= 9 for Normal Speed and
D
1
+
)S
2
)S
+
ATmega64A
S
M
(C)
F
189
= 4