ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 101

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.8
8160C–AVR–07/09
Timer/Counter Timing Diagrams
pare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing)
the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements.
The PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
Figure 14-8
Timer/Counter is a synchronous design and the timer clock (clk
enable signal. The figure shows the count sequence close to the MAX value.
Figure 14-11
when interrupt flags are set.
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 14-8. Timer/Counter Timing Diagram, no Prescaling
• OCR0 changes its value from MAX, like in
• The timer starts counting from a higher value than the one in OCR0, and for that reason
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Figure 14-8
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
and
show the same timing data, but with the prescaler enabled. The figures illustrate
contains timing data for basic Timer/Counter operation. The figure shows the
Figure 14-9
MAX - 1
Figure 14-7
contain timing data for the Timer/Counter operation. The
f
OCnPCPWM
MAX
OCn has a transition from high to low even though
Figure
=
----------------- -
N 510
f
clk_I/O
14-7. When the OCR0 value is MAX the
⋅
BOTTOM
T0
) is therefore shown as a clock
I/O
ATmega64A
should be replaced by
Figure 14-10
BOTTOM + 1
and
101
T0
)