ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 133

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11 16-bit Timer/Counter Register Description
15.11.1
15.11.2
8160C–AVR–07/09
TCCR1A –Timer/Counter1 Control Register A
TCCR3A – Timer/Counter3 Control Register A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the Output Compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting.
the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 15-2.
Bit
0x2F (0x4F)
Read/Write
Initial Value
Bit
(0x8B)
Read/Write
Initial Value
COMnA1/
COMnB1/
COMnC1
0
0
1
1
COM3A1
COM1A1
R/W
R/W
Compare Output Mode, non-PWM
7
0
7
0
COMnA0/
COMnB0/
COMnC0
COM3A0
COM1A0
0
1
0
1
R/W
R/W
6
0
6
0
COM3B1
COM1B1
Description
Normal port operation, OCnA/OCnB/OCnC disconnected.
Toggle OCnA/OCnB/OCnC on Compare Match.
Clear OCnA/OCnB/OCnC on Compare Match (Set output to low
level).
Set OCnA/OCnB/OCnC on Compare Match (Set output to high
level).
R/W
R/W
5
0
5
0
Table 15-2
COM3B0
COM1B0
R/W
R/W
4
0
4
0
COM3C1
COM1C1
shows the COMnx1:0 bit functionality when
R/W
R/W
3
0
3
0
COM3C0
COM1C0
R/W
R/W
2
0
2
0
WGM31
WGM11
R/W
R/W
1
0
ATmega64A
1
0
WGM30
WGM10
R/W
R/W
0
0
0
0
TCCR3A
TCCR1A
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