MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 634

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Debug Support
30.5
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial command
interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module.
Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM
commands, such as memory accesses, can be executed while the processor is running.
30.5.1
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation
requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of
priority:
30-16
28–22/
20–18/
28/12
27/11
26/10
12–6
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Bits
4–2
Background Debug Mode (BDM)
CPU Halt
Name
EPC
EDx
EAx
PCI
DI
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW
EDWL
EDWU Upper data word.
EDLL
EDLM
EDUM
EDUU
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other than the DBR
contents.
Enable address bits. Setting an EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR
to enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and
PBMR.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Data longword. Entire processor’s local data bus.
Lower data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR
and ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range defined
by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the ABLR.
Table 30-14. TDR Field Descriptions (continued)
Description
Freescale Semiconductor