MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 167

IC MPU 512K 80MHZ 256-MAPBGA

MCF5282CVM80

Manufacturer Part Number
MCF5282CVM80
Description
IC MPU 512K 80MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5282CVM80

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
Ram Memory Size
64KB
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Digital Ic Case Style
MAPBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an
instruction fetch access to any of these peripheral modules is attempted, the IPS bus cycle is immediately
terminated with an error.
8.6.3.3
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. Each of the
first two regions has a unique access control register associated with it. The other fourteen regions are in
reserved space; the access control registers for these regions are not implemented. Bits [29:26] of the
address select the specific GPACRn to be used for a given reference within the IPS address space. These
access control registers are 8 bits in width so that read, write, and execute attributes may be assigned to the
given IPS region.
Freescale Semiconductor
IPSBAR Offset
Grouped Peripheral Access Control Registers (GPACR0 & GPACR1)
Read/Write
The access control for modules with memory space protected by
PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access
control is not affected by GPACR0, even though the modules are mapped in
its 64-Mbyte address space.
Address
0x027
0x028
0x029
0x02a
0x02b
0x02d
0x02e
0x02c
Reset
Table 8-11. Peripheral Access Control Registers (PACRs) (continued)
Field
Figure 8-10. Grouped Peripheral Access Control Register (GPACR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
LOCK
R/W
7
PACR3
PACR4
PACR5
PACR6
PACR7
PACR8
Name
6–4
R
IPSBAR + 0x030, IPSBAR + 0x31
NOTE
3
0000_0000
ACCESS_CTRL1
UART2
DTIM0
DTIM2
INTC0
FEC0
I
2
ACCESS_CTRL
C
Modules Controlled
R/W
ACCESS_CTRL0
System Control Module (SCM)
DTIM1
DTIM3
INTC1
QSPI
0
8-15

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