MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 351

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.5.11 Full Duplex Flow Control
Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon
detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] set) with flow
control (RCR[FCE] set). The FEC detects a pause frame when the fields of the incoming frame match the
pause frame specifications, as shown in
frame should indicate that the frame is valid.
The receiver and microcontroller modules perform PAUSE frame detection. The microcontroller runs an
address recognition subroutine to detect the specified pause frame destination address, while the receiver
detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the
FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer
begins to increment. The pause timer uses the transmit backoff timer hardware for tracking the appropriate
collision backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is cleared
allowing MAC data frame transmission to resume. The receive flow control pause status bit
(TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow control pause
(TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets TCR[GTS] internally. When
the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts and the
pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally.
You must specify the desired pause duration in the OPD register.
Freescale Semiconductor
48-bit Destination Address
Table 17-37. Destination Address to 6-Bit Hash (continued)
16-bit PAUSE Duration
48-bit Source Address
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
16-bit Opcode
FDFF_FFFF_FFFF
DDFF_FFFF_FFFF
BDFF_FFFF_FFFF
9DFF_FFFF_FFFF
16-bit Type
Table 17-38. PAUSE Frame Field Specification
48-bit DA
Table
17-38. In addition, the receive status associated with the
6-bit Hash
0x0180_C200_0001 or Physical Address
(in hex)
0x3C
0x3D
0x3E
0x3F
0x0000 – 0xFFFF
0x8808
0x0001
Hash Decimal
Any
Value
60
61
62
63
Fast Ethernet Controller (FEC)
17-41