MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 548

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28.6.5
This subsection describes the QADC control registers.
28.6.5.1 QADC Control Register 0 (QACR0)
QACR0 establishes the QADC sampling clock (QCLK) with prescaler parameter fields and defines
whether external multiplexing is enabled. Typically, these bits are written once when the QADC is
initialized and not changed thereafter. The bits in this register are read anytime, write anytime (except
during stop mode).
28-10
14–13
Bit(s)
Address
Address
15
12
Reset
Reset
Reset
R/W:
Field
Field
R/W:
Field
R/W
Control Registers
MUX
R/W
15
—
Name
7
R
7
MUX
TRG
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 28-7. Port QB Data Direction Register (DDRQB)
QPR6
14
6
Figure 28-8. QADC Control Register 0 (QACR0)
6
Externally multiplexed mode. Configures the QADC for operation in externally
multiplexed mode, which affects the interpretation of the channel numbers and forces
the MA[1:0] signals to be outputs.
1 Externally multiplexed, up to 18 possible channels
0 Internally multiplexed, up to 8 possible channels
Reserved, should be cleared.
Trigger assignment. Determines the queue assignment of the ETRIG[2:1] signals.
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.
—
Table 28-4. QACR0 Field Descriptions
R
—
QPR5
13
5
5
IPSBAR + 0x19_000a, 0x19_000b
IPSBAR + 0x19_0009
TRG
QPR4
R/W
12
4
4
0000_0000
0000_0000
0001_0011
R
DDQB3
R/W
QPR3
Description
11
3
3
DDQB2
QPR2
2
2
—
R
DDQB1
QPR1
1
1
Freescale Semiconductor
DDQB0
QPR0
0
8
0