MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 514

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

General Purpose I/O Module
PORTnP/SETn bits are described in
26.3.2.4 Port Clear Output Data Registers (CLRn)
Clearing a CLRn register clears the corresponding bits in the PORTn register. Setting it has no effect.
Reading the CLRn register returns 0s.
Most PORTn registers have a full 8-bit implementation, as shown in
registers use fewer than eight bits. Their bit definitions are shown in
Figure
The CLRn registers are read/write accessible.
26-14
26-18.
Address
Address IPSBAR + 0x10_003C (CLRA), 0x10_003D (CLRB), 003E (CLRC), 0x10_003F (CLRD), 0x10_0040
Register
Reset
Reset
R/W:
R/W:
Field
Field
8-bit
7-bit
6-bit
4-bit
7-bit
6-bit
4-bit
CLRn7
(CLRE), 0x10_0041 (CLRF), 0x10_0042 (CLRG), 0x10_0043 (CLRH), 0x10_0044 (CLRJ),
Table 26-5. PORTnP/SETn (8-bit, 6-bit, and 4-bit) Field Descriptions
7
7
IPSBAR + 0x10_0037 (PORTTCP/SETTC), 0x10_0038 (PORTTDP/SETTD),
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 26-15. Port Clear Output Data Registers (8-bit)
Bits
Figure 26-14. Port Pin Data/Set Data Registers (4-bit)
7–0
6–0
5–0
3–0
7–6
7–4
7
CLRn6
0x10_0045 (CLRDD), 0x10_0046 (CLREH), 0x10_0047 (CLREL)
6
0000
—
—
Table
PORTxnP/SETxn
CLRn5
5
Name
26-5.
0x10_0039 (PORTUAP/SETUA)
—
CLRn4
4
4
0000_0000
Port x Pin Data/Set Data Bits
1 Port x pin state is 1 (read); set corresponding
0 Port x pin state is 0 (read)
Reserved, should be cleared.
R/W
PORTx bit (write)
PORTnP3/
CLRn3
SETn3
3
3
PORTnP2/
Figure
SETn2
CLRn2
Current Pin State
Description
2
2
Figure
R/W
26-15. The remaining PORTn
PORTnP1/
CLRn1
SETn1
26-16,
1
1
Freescale Semiconductor
Figure
PORTnP0/
SETn0
CLRn0
0
0
26-17, and