MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet
MCF5282CVM80
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MCF5282CVM80 Summary of contents
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MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual Devices Supported: MCF5214 MCF5216 MCF5280 MCF5281 MCF5282 Document Number: MCF5282UM Rev. 3 2/2009 ® ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...
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Enhanced Multiply-Accumulate Unit (EMAC) ColdFire Flash Module (CFM) System Control Module (SCM) External Interface Module (EIM) Synchronous DRAM Controller Module Fast Ethernet Controller (FEC) Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) Modules Queued Serial Peripheral Interface Module (QSPI) ...
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Overview 1 ColdFire Core 2 Enhanced Multiply-Accumulate Unit (EMAC) 3 Cache 4 Static RAM (SRAM) 5 ColdFire Flash Module (CFM) 6 Power Management 7 System Control Module (SCM) 8 Clock Module 9 Interrupt Controller Modules 10 Edge Port Module (EPORT) ...
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... Condition Code Register (CCR 2-6 2.2.5 Program Counter (PC 2-7 2.2.6 Cache Control Register (CACR 2-7 2.2.7 Access Control Registers (ACRn 2-7 2.2.8 Vector Base Register (VBR 2-7 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 1 Overview Chapter 2 ColdFire Core v ...
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... Mask Register (MASK 3-5 3.2.3 Accumulator Registers (ACC0– 3-6 3.2.4 Accumulator Extension Registers (ACCext01, ACCext23 3-7 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.1.1 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev Chapter 3 Freescale Semiconductor ...
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... Flash Base Address Register (FLASHBAR 6-5 6.3.3 CFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.4.1 CFM Configuration Register (CFMCR 6-8 6.3.4.2 CFM Clock Divider Register (CFMCLKD 6-9 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 4 Cache Chapter 5 Static RAM (SRAM) Chapter 6 ...
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... ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.2 Static Random-Access Memory (SRAM 7-6 7.3.2.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.4 System Control Module (SCM 7-7 7.3.2.5 SDRAM Controller (SDRAMC 7-7 7.3.2.6 Chip Select Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 viii Chapter 7 Power Management Freescale Semiconductor ...
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... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3.1 Master Privilege Register (MPR 8-13 8.6.3.2 Peripheral Access Control Registers (PACR0–PACR8 8-13 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 8 System Control Module (SCM) ix ...
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... Alternate Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.11 Loss of Clock in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 10.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev Chapter 9 Clock Module Chapter 10 Interrupt Controller Modules Freescale Semiconductor ...
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... Chip Select Address Registers (CSAR0–CSAR6 12-6 12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6 12-6 12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6 12-7 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 11 Edge Port Module (EPORT) Chapter 12 ...
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... SDRAM Write Enable (DRAMW 14-21 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0 14-21 14.2.2.5 SDRAM Clock Enable (SCKE 14-22 14.2.3 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.1 Reset In (RSTI 14-22 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xii Chapter 13 Chapter 14 Signal Descriptions Freescale Semiconductor ...
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... Clear-to-Send (UCTS[1:0 14-26 14.2.10.4 Request-to-Send (URTS[1:0 14-27 14.2.11General Purpose Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11.1 GPTA[3: 14-27 14.2.11.2 GPTB[3: 14-27 14.2.11.3 External Clock Input (SYNCA/SYNCB 14-27 14.2.12DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor xiii ...
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... Positive Supply (VDD 14-32 14.2.16.9 Ground (VSS 14-32 Synchronous DRAM Controller Module 15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 Block Diagram and Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 SDRAM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xiv Chapter 15 Freescale Semiconductor ...
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... Channel Initialization and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.1 Channel Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.2 Programming the DMA Controller Module . . . . . . . . . . . . . . . . . . . 16-12 16.5.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.1 Auto-Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.2 Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.5 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 16 DMA Controller Module xv ...
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... Driver/DMA Operation with Buffer Descriptors . . . . . . . . . . . . . . . . 17-25 17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD 17-27 17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD 17-29 17.5.2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xvi Chapter 17 Fast Ethernet Controller (FEC) Freescale Semiconductor ...
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... PIT Control and Status Register (PCSRn 19-3 19.2.2 PIT Modulus Register (PMRn 19-5 19.2.3 PIT Count Register (PCNTRn 19-5 19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 18 Watchdog Timer Module Chapter 19 xvii ...
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... Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.6.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.1 GPT Channel Interrupts (CnF 20-21 20.8.2 Pulse Accumulator Overflow (PAOVF 20-22 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xviii Chapter 20 Freescale Semiconductor ...
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... Command RAM Registers (QCR0–QCR15 22-8 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.2 Transmit RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 21 DMA Timers (DTIM0–DTIM3) Chapter 22 xix ...
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... Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev Chapter 23 UART Modules Freescale Semiconductor ...
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... The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3 Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1.1 Common Fields for Extended and Standard Format Frames . . . . . . 25-5 25.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter Interface Chapter 25 ...
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... Receive Error Counter (RXECTR 25-29 25.5.12FlexCAN Transmit Error Counter (TXECTR 25-30 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xxii Chapter 26 General Purpose I/O Module Freescale Semiconductor ...
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... Chip Configuration Register (CCR 27-4 27.5.3.2 Reset Configuration Register (RCON 27-5 27.5.3.3 Chip Identification Register (CIR 27-6 27.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 27 xxiii ...
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... Conversion Command Word Table (CCW 28-24 28.6.8 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.6.8.1 Right-Justified Unsigned Result Register (RJURR 28-27 28.6.8.2 Left-Justified Signed Result Register (LJSRR 28-27 28.6.8.3 Left-Justified Unsigned Result Register (LJURR 28-28 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xxiv Chapter 28 Freescale Semiconductor ...
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... Analog Supply Filtering and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-61 28.9.5 Accommodating Positive/Negative Stress Conditions . . . . . . . . . . . . . . . . . 28-62 28.9.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-64 28.9.7 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-66 28.9.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . . . . . . . . . . 28-67 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor xxv ...
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... Address Attribute Trigger Register (AATR 30-7 30.4.3 Address Breakpoint Registers (ABLR, ABHR 30-9 30.4.4 Configuration/Status Register (CSR 30-10 30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR 30-12 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xxvi Chapter 29 Reset Controller Module Chapter 30 Debug Support Freescale Semiconductor ...
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... JTAG_CFM_CLKDIV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4.2.5 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4.2.6 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.5.1 JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.5.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.5.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Chapter 31 xxvii ...
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... Serial Management Channel Timing (EMDIO and EMDC 33-23 33.14DMA Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.15QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.16JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-25 33.17Debug AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-27 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xxviii Chapter 32 Mechanical Data Chapter 33 Electrical Characteristics Freescale Semiconductor ...
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... B.5 Changes Between Rev. 2.1 and Rev. 2 B-7 B.6 Changes Between Rev. 2.2 and Rev. 2 B-7 B.7 Changes Between Rev. 2.3 and Rev B-8 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Appendix A Register Memory Map Appendix B Revision History ...
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... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 xxx Freescale Semiconductor ...
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... Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A . Patterson and John L. Hennessy. ColdFire Documentation ColdFire documentation is available from the sources listed on the back cover of this manual, as well as our web site, http://www.freescale.com/coldfire. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor xxxi ...
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... Application notes — These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire. ...
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... On-chip transmit and receive FIFOs — Built-in dedicated DMA controller MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Figure 1-1. The main features are as follows: 1-1 ...
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... Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev bus Freescale Semiconductor ...
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... Two 4-channel general purpose timers — Four 16-bit input capture/output compare channels per timer — 16-bit architecture — Programmable prescaler — Pulse widths variable from microseconds to seconds — Single 16-bit pulse accumulator MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Overview 1-3 ...
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... Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus — seven chip selects available — Byte/write enables (byte strobes) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 1-4 Freescale Semiconductor ...
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... Up to 134 bits of general purpose I/O for MCF5214/6 — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system-level board testing MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Overview 1-5 ...
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... UART1 UART2 Serial Serial Serial Modules I/O I/O I/O (DTIM0– General General Purpose Purpose QADC Timer A Timer B Test Controller Debug Module 64K SRAM EMAC 2-Kbyte DMA Timer Watchdog Timer Module DTIM3) PIT Timers QSPI FlexCAN (PIT0– PIT3) Freescale Semiconductor ...
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... FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 1-1. Cache Configuration Tag Address Data Array Address ...
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... Watchdog Timer (CWT), and the system control registers and logic. Specifically, the system control includes the internal peripheral system base address register (IPSBAR), the processor’s dual-port RAM MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 1-8 NOTE Freescale Semiconductor ...
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... Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Overview 1-9 ...
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... Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 1-10 Freescale Semiconductor ...
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... DMA Controller The Direct Memory Access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels (DMA0–DMA3) that allow MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Overview 1-11 ...
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... C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 1-12 NOTE Freescale Semiconductor ...
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... The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Overview 1-13 ...
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... Overview MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 1-14 Freescale Semiconductor ...
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... AGEX The instruction fetch pipeline (IFP two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Instruction Address Generation ...
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... Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23). MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-2 Table 2-1 lists the processor registers. Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC : Freescale Semiconductor ...
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... MAC Accumulator 0,1 Extension Bytes (ACCext01) 0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 0x80E Condition Code Register (CCR) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Width Access Reset Value (bits) Supervisor/User Access Registers 32 R/W 0xCF20_6080 32 ...
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... Written with Reset Value Section/Page MOVEC Contents of No 2.2.5/2-7 location 0x0000_0004 0x0000_0000 Yes 2.2.6/2-7 See Section Yes 2.2.7/2-7 Contents of No 2.2.3/2-5 location 0x0000_0000 0x0000_0000 Yes 2.2.8/2-7 0x27-- No 2.2.9/2-8 0x0000_0000 Yes 2.2.10/2-8 See Section Yes 2.2.10/2-8 Access: User read/write BDM read/write Freescale Semiconductor 0 ...
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... A7 register. The SSP is loaded during reset exception processing with the contents of location 0x0000_0000. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Address Figure 2-3. Address Registers (A0–A6) NOTE ...
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... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-6 Address — — Figure 2-5. Condition Code Register (CCR) Table 2-2. CCR Field Descriptions Description Access: A7: User or BDM read/write OTHER_A7: Supervisor or BDM read/write Access: User read/write BDM read/write — — Freescale Semiconductor — ...
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... BDM: 0x801 (VBR Base Address W Reset MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Address Figure 2-6. Program Counter Register (PC) Section 4.2.1, “Cache Control Register (CACR).” Figure 2-7. Vector Base Register (VBR) ColdFire Core Access: User read/write ...
Page 54
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev Figure 2-8. Status Register (SR) Table 2-3. SR Field Descriptions Description (CCR)”. (FLASHBAR)”. Access: Supervisor read/write BDM read/write Condition Code Register (CCR — — — — and Section 6.3.2, Freescale Semiconductor 0 C — ...
Page 55
... In these diagrams, the internal structure of the instruction fetch and operand execution pipelines is shown: IAG +4 Figure 2-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 2-1, the non-Harvard architecture of the processor is readily apparent. IC Core Bus Address FIFO ...
Page 56
... For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-10 DSOC AGEX Core Bus Address Core Bus Write Data Freescale Semiconductor ...
Page 57
... The following example move.l <mem>y,Rx in Figure 2-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Operand Execution Pipeline DSOC AGEX Rx Ry Figure 2-11. V2 OEP Register-to-Register ...
Page 58
... Figure 2-12. V2 OEP Embedded-Load Part 1 Operand Execution Pipeline DSOC Rx <mem>y Figure 2-13. V2 OEP Embedded-Load Part 2 Figure 2-14 AGEX <ea>y Core Bus Address Core Bus Write Data AGEX new Rx Core Bus Address Core Bus Write Data where the effective address is of the form Freescale Semiconductor ...
Page 59
... Read Data The pipeline timing diagrams of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Operand Execution Pipeline DSOC Ax Ry d16 Figure 2-14 ...
Page 60
... ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-14 OC next next AGEX OC next EX op read op write Freescale Semiconductor ...
Page 61
... The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description Section 2.3.4.1, ColdFire Core ...
Page 62
... Next 0x064–0x07C — 2-16, the processor uses a simplified for details on Assignment Initial program counter Access error Address error Illegal instruction Divide by zero Reserved Privilege violation Trace Debug interrupt Reserved Format error Reserved Spurious interrupt Reserved Freescale Semiconductor ...
Page 63
... There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Stacked Vector ...
Page 64
... The NOP instruction can collect access errors for writes. This instruction delays its MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-18 Table 2-7. Fault Status Encodings Definition Reserved Error on instruction fetch Reserved Reserved Error on operand write Attempted write to write-protected space Reserved Error on operand read Reserved Reserved Freescale Semiconductor ...
Page 65
... Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) 0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) 0x8 Logical OR (OR) 0x9 Subtract (SUB), Subtract Extended (SUBX) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor OpMode Table 2-8. ColdFire Opword Line Definition ...
Page 66
... The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-20 Instruction Class Freescale Semiconductor ...
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... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor for a detailed explanation of this exception, which is generated in ColdFire Core ...
Page 68
... PC access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-22 for details. ,” for details on the interrupt controller. NOTE Freescale Semiconductor ...
Page 69
... FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. FPU 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor ...
Page 70
... Configurable cache associativity. CCAS 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 2-24 Description CCSZ Description Access: User read-only BDM read-only FLASHSZ SRAMSZ Freescale Semiconductor ...
Page 71
... Each timing entry is presented as C(R/W) where: • the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description ColdFire Core 2-25 ...
Page 72
... Table 2-11. Misaligned Operand References Bus Size Operations Word Byte, Byte Long Byte, Word, Byte 10 Long Word, Word NOTE Additional C(R/W) 2(1/0) if read 1(0/1) if write 3(2/0) if read 2(0/2) if write 2(1/0) if read 1(0/1) if write Table 2-13 lists timings for MOVE.L. Freescale Semiconductor ...
Page 73
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor equals ET with {<ea> = (d16,An)} equals ET with {<ea> = (d8,An,Xi*SF)} Destination (Ax) (Ax)+ -(Ax) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 3(1/1) ...
Page 74
... Freescale Semiconductor #xxx — — — — — — — — — — — — — — 1(0/0) 1(0/0) 1(0/0) #xxx — ...
Page 75
... SUB.L <ea>,Rx 1(0/0) SUB.L Dy,<ea> — SUBI.L #imm,Dx 1(0/0) SUBQ.L #imm,<ea> 1(0/0) SUBX.L Dy,Dx 1(0/0) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) — — — — — — — — 4(1/1) ...
Page 76
... Freescale Semiconductor #xxx — — — — — 1(0/0) — 2 7(0/0) — — — — — — 5(0/1) 3 3(0/0) 15(1/2) — ...
Page 77
... MULU.W <ea> Effective address of (d16,PC) not supported 2 Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Effective Address Rn (An) (An)+ -(An) (d16,An) 1(0/0) — ...
Page 78
... Forward Forward Backward Taken Not Taken 3(0/0) 1(0/0) (d8,An,Xi*SF) xxx.wl (d8,PC,Xi*SF) — — — — 4(0/0) 3(0/0) 4(0/1) 3(0/1) — — — — — — Backward Taken Not Taken 2(0/0) 3(0/0) Freescale Semiconductor #xxx — — — — — — ...
Page 79
... The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor (Figure 3-1). 3-1 ...
Page 80
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-2 Operand Y Operand X X Shift 0,1,- Accumulator( – – ∑ ∑ – + – Equation 3 simple, four-tap FIR filter, shown – + Equation 3- – + – Freescale Semiconductor Eqn. 3-1 Eqn. 3-2 ...
Page 81
... MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly. Bit 11: Accumulator 3 ... Bit 8: Accumulator 0 MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 3-1. EMAC Memory Map Width Register Figure 3-2. MAC Status Register (MACSR) Table 3-2. MACSR Field Descriptions ...
Page 82
... MULS and MULU instructions. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-4 Description Section 3.3.1.1, “Rounding”. The resulting 16-bit value is stored in the -31 for 32-bit fractions. See Section 3.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is Section 3.3.4, “Data Freescale Semiconductor ...
Page 83
... For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows: mac.sz Ry,RxSF,<ea>yand ,Rw MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description F/I R/T Operational Modes ...
Page 84
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-6 {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF0x, MASK} Figure 3-3. Mask Register (MASK) Table 3-4. MASK Field Descriptions Description Access: User read/write BDM read/write MASK Freescale Semiconductor ...
Page 85
... Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Accumulator Table 3-5. ACC0–3 Field Descriptions Description ACC0L Table 3-6. ACCext01 Field Descriptions Description Enhanced Multiply-Accumulate Unit (EMAC) ...
Page 86
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-8 ACC2L Table 3-7. ACCext23 Field Descriptions Description Access: User read/write BDM read/write ACC3U ACC3L Freescale Semiconductor 1 0 ...
Page 87
... Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6: unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor OperandY 32 X OperandX 32 40 ...
Page 88
... Let the high-order 16 bits named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-10 ). The lsbs of the 48-bit accumulator move.l ACCx,Rx Freescale Semiconductor ...
Page 89
... This code performs the EMAC state restore: EMAC_state_restore: MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Enhanced Multiply-Accumulate Unit (EMAC) /* R0.L = 0x8000 */ ; save the macsr ; zero the register to ... ; disable rounding in the macsr ; save the accumulators ...
Page 90
... Writes the contents of an accumulator to a CPU register Copies a 48-bit accumulator Writes a value to MACSR Write the contents of MACSR to a CPU register Write the contents of MACSR to the CCR Writes a value to the MASK register Writes the contents of the MASK to a CPU register operand Description Freescale Semiconductor ...
Page 91
... The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Mnemonic operand Writes the contents of accumulator 0,1 extension bytes into a ...
Page 92
... ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-14 Equation 3- – ∑ ⋅ ) – – ⋅ = – – -31 ). (MACSR)” The a a ... a N-1 N-2 N-3 2 Eqn. 3-3 (N-1) . Freescale Semiconductor (N- -15 ); ...
Page 93
... MACSR.PAVn = 1 MACSR (inst == MSAC and and then if (product[63 else if (MACSR.OMC == 1) } MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor (product[63:39] != 0xffff_ff_1)) /* product overflow */ MACSR.OMC == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 then /* overflowed MAC, saturationMode enabled */ if (product[63 ...
Page 94
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-16 /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ saturationMode enabled */ if (result[47 then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 /* signed fractionals */ /* sign-extend */ 0x0000} Freescale Semiconductor ...
Page 95
... Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/ MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor then product[63:24] = product[63:24 (operandX[31:0] == 0x8000_0000)) saturationMode enabled */ if (result[47 then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000 ...
Page 96
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-18 /* product overflow */ MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff /* zero-fill upper byte */ /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ Freescale Semiconductor ...
Page 97
... ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR else MACSR (ACCx[47:32] == 0x0000) then MACSR. else MACSR. break; } MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff 3-19 ...
Page 98
... Enhanced Multiply-Accumulate Unit (EMAC) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 3-20 Freescale Semiconductor ...
Page 99
... This address field is compared to bits [31: or data-only configurations and to bits [31: bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 128 -entry tag array (containing addresses and × 32 bits. ...
Page 100
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev Line Buffer Address = Fill Hit TAG 127 = Tag Hit Figure 4-1. 2-Kbyte Cache Block Diagram External Data[31: Line Buffer Storage MUX DATA 511 MUX Local Data Bus Table 4-1 below shows the memory map Freescale Semiconductor ...
Page 101
... DISD (disable data caching) bits, control the cache configuration. 0 Cache disabled 1 Cache enabled Table 4-3 describes cache configuration. 30–29 Reserved, must be cleared. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 4-1. Cache Memory Map Width Register (bits Figure 4-2, is shown as read/write ...
Page 102
... Disable burst fetches on non-cacheable accesses 1 Enable burst fetches on non-cacheable accesses MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 4-4 Description Table 4-4 describes how to set the cache invalidate all bit. Table 4-4 describes how to set the cache invalidate all bit. 4-7. Freescale Semiconductor ...
Page 103
... Table 4-4 shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache invalidate all bit (CACR[CINV]). MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description Attributes. Section 2.2.3, “Supervisor/User Stack Pointers (A7 and Table 4-6 for external fetch size based on miss address and CLNF. ...
Page 104
... Invalidate only 1 KByte instruction cache Data Cache 1 Split Instruction/ No invalidate Data Cache x Instruction Cache Invalidate 2 KByte instruction cache x Data Cache Invalidate 2 KByte data cache NOTE – – Operation Figure 4-3, is shown as read/write. At Access: Supervisor write-only BDM read/write BWE – – Freescale Semiconductor – ...
Page 105
... Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 4-5. ACRn Field Descriptions Description Cache ...
Page 106
... Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the cache can be enabled. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 4-8 10 :4] of the source address register is invalidated, provided CACR[CPDI] 10 that selects Freescale Semiconductor ...
Page 107
... Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 4-6 shows the relationship between the CLNF bits, Table 4-6. Initial Fetch Offset vs. CLNF Bits ...
Page 108
... All instruction fetches are word or longword in size, and not loaded into the line-fill buffer Non-cacheable Instruction fetch size is defined by loaded into the line-fill buffer, but are never written into the memory array. Description Table 4-6 and contents of the Table 4-6 and Freescale Semiconductor ...
Page 109
... RAMBAR, and return zeroes when read from the debug module. • The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor (SCM)” for more information. 5-1 ...
Page 110
... Table 5-1. SRAM Base Address Register Description Upper Bank PRI[1:2] Priority 00 DMA Accesses 01 DMA Accesses 10 CPU Accesses 11 CPU Accesses (RAMBAR).” Figure 5 C Lower Bank Priority DMA Accesses CPU Accesses DMA Accesses CPU Accesses Section 8.4.2, “Memory Base Address Freescale Semiconductor ...
Page 111
... EQU $20000000 RAMVALID EQU $00000001 move.l #RAMBASE+RAMVALID,D0 movec.l D0, RAMBAR MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description Section 5.3.4, “Power ;set this variable to $20000000 ;load RAMBASE + valid bit into D0. ;load RAMBAR and enable SRAM Static RAM (SRAM) 5-3 ...
Page 112
... Both Code And Data MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 5-4 ;load pointer to SRAM ;load loop counter into D0 ;clear 4 bytes of SRAM ;decrement loop counter ;if done, then exit; else continue looping RAMBAR[7:0] Code Only Data Only 0x2B 0x35 0x21 Freescale Semiconductor ...
Page 113
... Auto-sense amplifier timeout for low-power, low-frequency read operations Enabling Flash security will disable BDM communications. When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE ) used for all module operations DD NOTE ...
Page 114
... An erased Flash bit reads 1 and a programmed Flash bit reads 0. The CFM features a sense amplifier timeout (SATO) block that automatically reduces current consumption during reads at low system clock frequencies. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 6-2 contains the Flash physical blocks, the ColdFire Flash bus and IP Freescale Semiconductor ...
Page 115
... Mass Erase Block 0 (256 Kbytes) = Flash Physical Block 0 and Flash Physical Block 1. Mass Erase Block 1 (256 Kbytes) = Flash Physical Block 2 and Flash Physical Block 3 (MCF5282 and MCF5216 only) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Internal Bus Flash Physical ...
Page 116
... A similar mechanism is available to control Flash Physical Block 3 3H[31] 3L[31] Memory Memory Array 3H Array 3L 3H[0] 3L[0] Flash Physical Block 1 1H[31] 1L[31] Memory Memory Array 1H Array 1L 1H[0] 1L[0] Each memory array = 64 Kbytes (16 bits wide × 32K) (32 bits wide × 32K) Freescale Semiconductor ...
Page 117
... FLASHBAR located in the processor’s CPU space will be invalid and it must be initialized with the valid bit set before the CPU (or modules) can access the on-chip Flash. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 6-1 describes each byte used in this field. Table 6-1. CFM Configuration Field ...
Page 118
... Figure 6-3. Flash Base Address Register (FLASHBAR) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 6-6 NOTE NOTE (CCM)” for more details. When the default reset 0000_0000_0000_0000 R — WP — 0000_0001_0010_000 R CPU + 0xC04 (CCM)”). Chapter 27, “Chip — C R/W Chapter 27, Freescale Semiconductor See Note ...
Page 119
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 6-2. FLASHBAR Field Descriptions Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’ ...
Page 120
... PVIOL interrupts disabled. Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit enables an interrupt in case the access error flag, ACCERR, is set interrupt will be requested whenever the ACCERR flag is set. 0 ACCERR interrupts disabled. 1 Bits 7–0 Access — Freescale Semiconductor ...
Page 121
... PRDIV8 5–0 DIV MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 6-4. CFMCR Field Descriptions Description Command buffer empty interrupt enable. The CBEIE bit is readable and writable. CBEIE enables an interrupt request when the command buffer for the Flash physical blocks is empty ...
Page 122
... Section 6.4.3.1, “Setting the CFMCLKD NOTE NOTE See Note R SEC See Note R IPSBAR + 0x1D_0008 Table 6-6. CFMSEC Field Descriptions Description Enable back door key to security 1 Back door to Flash is enabled. 0 Back door to Flash is disabled. Flash security status 1 Flash security is enabled 0 Flash security is disabled — Freescale Semiconductor 16 0 ...
Page 123
... SEC[15:0] The security features of the CFM are described in MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 6-6. CFMSEC Field Descriptions Description Reserved. Should be cleared. Security field. The SEC bits define the security state of the device; see below. ...
Page 124
... PROT See Note R/W IPSBAR + 0x1D_0010 Table 6-7. CFMPROT Field Descriptions Description Sector protection. Each Flash logical sector can be protected from program and erase operations by setting its corresponding PROT bit. 1 Logical sector is protected. 0 Logical sector is not protected. NOTE 16 0 Freescale Semiconductor ...
Page 125
... Note: The CFMPROT register is loaded at reset from the Flash Supervisor/user Space Restrictions longword stored at the array base address + 0x0000_040C. Figure 6-9. CFM Supervisor Access Register (CFMSACC) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor SECTOR 31 • • • ...
Page 126
... When an array sector is mapped into both data and program address space both data and program accesses are allowed. 1 Logical sector is mapped in data address space. 0 Logical sector is mapped in data and program address space 16 0 Figure 6-8 for . Freescale Semiconductor ...
Page 127
... Name 7 CBEIF 6 CCIF 5 PVIOL 4 ACCERR 3 — MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 6 5 CCIF PVIOL ACCERR — 1100_0000 R IPSBAR + 0x1D_0020 NOTE Table 6-10. CFMUSTAT Field Descriptions Description Command buffer empty interrupt flag. The CBEIF flag indicates that the command buffer for the interleaved Flash physical blocks is empty and that a new command sequence can be started ...
Page 128
... Command. Valid Flash user mode commands are shown in command in user mode other than those listed in flag in CFMUSTAT. Name RDARY1 PGM PGERS MASERS PGERSVER 0 Table 6-12. Writing a Table 6-12 will set the ACCERR Description Erase verify (all 1s) Longword program Page erase Mass erase Page erase verify Freescale Semiconductor ...
Page 129
... Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result and discard any fraction. Do not round the result. 3. Thus the Flash state machine clock will be: MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor f SYS DIV[5:0] = ...
Page 130
... MHz: SYS f SYS DIV[5: 200kHz (PRDIV8 x 7)) 66 MHz = 400 kHz 7)) f SYS = CLK 2 x (DIV[5: (PRDIV8 x 7)) 66 MHz = 7)) CLK WARNING NOTE Operations”). = 20 = 196.43 kHz to 196.43 kHz which is a valid frequency between CLK CLK . CLK Freescale Semiconductor ...
Page 131
... Mass erase 0x06 Page erase verify MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE Commands.” NOTE Figure 6-13. The flow is similar for the erase and Table 6-13. Flash User Commands Description Verify that all 256 Kbytes of Flash from two interleaving physical blocks are erased ...
Page 132
... CBEIF BIT TO CFMUSTAT READ CFMUSTAT YES PVIOL WRITE 0x20 TO CLEAR SET? CFMUSTAT PVIOL BIT NO YES ACCERR WRITE 0x10 TO CLEAR SET? CFMUSTAT ACCERR BIT NO YES CBEIF SET? NO READ CFMUSTAT CCIF NO SET? YES EXIT Figure 6-13. Example Program Algorithm YES NEXT WRITE? NO Freescale Semiconductor ...
Page 133
... Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor (CFMPROT)”). NOTE WARNING ColdFire Flash Module (CFM) ...
Page 134
... The CFM may be unsecured via one of two methods: 1. Executing a back door access scheme. 2. Passing an erase verify check. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 6-22 NOTE NOTE Freescale Semiconductor ...
Page 135
... The CFM module can request an interrupt when all commands are completed or when the address, data, and command buffers are empty. Interrupt Source Command, data and address buffers empty MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE Table 6-14 shows the CFM interrupt mechanism. Table 6-14. CFM Interrupt Sources Interrupt Flag ...
Page 136
... ColdFire Flash Module (CFM) Table 6-14. CFM Interrupt Sources (continued) Interrupt Source All commands are completed Access error MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 6-24 Interrupt Flag Local Enable CCIF CCIE (CFMUSTAT) (CFMCR) ACCERR AEIE (CFMUSTAT) (CFMCR) Freescale Semiconductor ...
Page 137
... The PMM programming model consists of one register: • The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 7-1 ...
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... LPICR[XLPM_IPL[2:0]]. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-2 Bits 23–16 Bits 15–8 Core Watchdog Low-Power 2 Control Register Interrupt Control (CWCR) Register (LPICR) 3 Reserved NOTE 1 Bits 7–0 Access Core Watchdog S Service Register (CWSR) Low-Power Control S Register (LPCR) Freescale Semiconductor ...
Page 139
... Reserved, should be cleared. XLPM_IPL[2:0] 000 001 010 011 100 101 11x MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE XLPM_IPL 0 1/0 0 R/W IPSBAR + 0x012 Table 7-2. LPICR Field Descriptions Description Table Table 7-3 ...
Page 140
... RCR[LVDE] bit is a logic 0. 1 VREG Pseudo-Standby mode (LVD enabled on power down request). 0 VREG Standby mode (LVD disabled on power down request). Reserved, should be cleared. Table 7-5. Low-Power Modes LPMD[1: — LVDSE — Table 7-5 illustrates Mode STOP WAIT DOZE RUN Freescale Semiconductor ...
Page 141
... An interrupt request which has been enabled at the module of the interrupt’s origin 7.3.1.1 Run Mode Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Operation During Stop Mode CLKOUT PLL Enabled Enabled ...
Page 142
... The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 7.3.2.2 Static Random-Access Memory (SRAM) SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-6 NOTE (SDRAMC)” for more Freescale Semiconductor ...
Page 143
... DSR becomes set. The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Modes” for the core Watchdog interrupt to bring the part out of NOTE ...
Page 144
... DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-8 Freescale Semiconductor ...
Page 145
... When the CPU is inactive, a software reset cannot be generated to exit any low-power mode. 7.3.2.16 Chip Configuration Module The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Power Management 7-9 ...
Page 146
... When exiting these modes, the PIT resumes operation from the stopped value the responsibility of software to avoid erroneous operation. When not stopped, the PIT may generate an interrupt to exit the low-power modes. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-10 Freescale Semiconductor ...
Page 147
... Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Power Management 7-11 ...
Page 148
... The following are conditions for the automatic shut-off of FlexCAN clocks: • No Rx/Tx frame in progress. • No moving of Rx/Tx frames between SMB and MB and no Tx frame is pending for transmission in any MB. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-12 Freescale Semiconductor ...
Page 149
... Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE Power Management 7-13 ...
Page 150
... Yes Enabled Yes 2 Yes Stopped No No Enabled Yes Enabled Yes No Stopped No No Stopped Yes Program Yes 2 2 Yes Stopped Yes 3 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped Yes Enabled Yes No Enabled No Freescale Semiconductor ...
Page 151
... The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Power Management 7-15 ...
Page 152
... Power Management MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 7-16 Freescale Semiconductor ...
Page 153
... System bus master arbitration programming model (MPARK) • System access control unit (SACU) programming model — Master privilege register (MPR) — Peripheral access control registers (PACRs) — Grouped peripheral access control registers (GPACR0, GPACR1) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 8-1 ...
Page 154
... GPACR0 GPACR1 — — — — — — Chapter 7, “Power Management." NOTE 8-1. All the registers in the SCM are [15:8] [7:0] 1 LPICR CWSR — PACR2 PACR3 PACR5 PACR6 PACR8 — — — — — — — — — Freescale Semiconductor ...
Page 155
... MOVEC instruction at CPU space address 0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE — — ...
Page 156
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev 0000_0000_0000_0000 R BDE 0000_0000_0000_0000 R/W IPSBAR + 0x008 Table 8-3. RAMBAR Field Description Description Section 5.3.1, “SRAM Base Address Register NOTE (SRAM)” for more information — (RAMBAR).” Figure 8-2. Section 5.3.1, “SRAM Base Address Freescale Semiconductor 16 0 ...
Page 157
... The core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous ColdFire devices. However, there is a second watchdog timer available that has new features. See “Watchdog Timer MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor NOTE Module”) provides indication of all reset — ...
Page 158
... If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 8 (ICR8) of INTC0. 1 Reserved; do not use. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev CWRI CWT[2:0] CWTA 0000_0000 R/W IPSBAR + 0x011 Table 8-5. CWCR Field Description Description CWTAVAL CWTIC Freescale Semiconductor ...
Page 159
... The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which four MBus masters (M0–M3 in The function of the arbitration logic is described in this section. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor CWT Time-Out Period CWT 9 ...
Page 160
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 8-8 “back door” to SRAM and Flash SRAM1 MPARK M0 M2 EIM MARB Internal Modules M1 SDRAMC M3 Figure 8-6. Arbiter Module Functions RAMBAR Freescale Semiconductor ...
Page 161
... Master 3 (M3): Fast Ethernet Controller (Not used for the MCF5216 and MCF5214) • Master 2 (M2): 4-channel DMA • Master 1 (M1): Internal Bus Master (not used in normal user operation) • Master 0 (M0): V2 ColdFire Core MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor System Control Module (SCM) 8-9 ...
Page 162
... Reserved, should be cleared. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTY 0011_0000_1110_0001 R LCKOUT_TIME 0000_0000_0000_0000 R/W IPSBAR + 0x01C Table 8-6. MPARK Field Description Description — Freescale Semiconductor 16 0 ...
Page 163
... If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module not accessed. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description NOTE System Control Module (SCM) ...
Page 164
... Memory Map/Register Definition The memory map for the SACU program-visible registers within the System Control Module (SCM) is shown in Figure 8-7. The MPR, PACR, and GPACRs are 8 bits in width. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 8-12 Freescale Semiconductor ...
Page 165
... Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single PACR defines the access level for each of the two modules. These modules only support operand reads MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 8-7. SACU Register Memory Map [23:20] ...
Page 166
... Read/Write 101 Read/Write Read 110 Read/Write Read/Write 111 No Access No Access Name ACCESS_CTRL1 PACR0 PACR1 PACR2 8-9. For a list of PACRs and the modules 3 2 ACCESS_CTRL0 Table 8-10. Table 8-10. User Mode Modules Controlled ACCESS_CTRL0 SCM SDRAMC EIM DMA UART0 UART1 Freescale Semiconductor 0 ...
Page 167
... GPACR0, even though the modules are mapped in its 64-Mbyte address space. 7 Field LOCK Reset Read/Write R/W Address Figure 8-10. Grouped Peripheral Access Control Register (GPACR) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Modules Controlled Name ACCESS_CTRL1 PACR3 UART2 2 PACR4 I C — ...
Page 168
... Table 8-12. GPACR Field Descriptions Description Table Supervisor Mode No Access No Access Read No Access Read / Write Read Read / Write No Access No Access No Access Read / Execute No Access Read / Write / Execute Read / Execute Read Execute 8-13. Table 8-13. Table 8-14 shows the User Mode Freescale Semiconductor ...
Page 169
... GPACR1 0x0400_0000– 0x07FF_FFFF MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 8-14. GPACR Address Space Space Protected (IPSBAR Offset) Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) CFM (Flash module’ ...
Page 170
... System Control Module (SCM) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 8-18 Freescale Semiconductor ...
Page 171
... The post divider is not active. 9.2.3 External Clock Mode In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 9-1 ...
Page 172
... Exit not caused by clock module, but clock sources are re-enabled and normal clocking Normal Table 9-1 shows the clock module Mode Exit clocking resumes upon mode exit clocking resumes upon mode exit resumes upon mode exit Exit not caused by clock module Freescale Semiconductor ...
Page 173
... EXTAL XTAL EXTERNAL CLOCK OSC STPMD[1:0] STOP MODE MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor CLKMOD[1:0] RSTOUT MFD REFERENCE CLOCK PLL PLLREF LOCEN CLKGEN PLLSEL DISCLK PLLMODE Figure 9-1. Clock Module Block Diagram Clock Module CLKOUT LOCKS ...
Page 174
... Descriptions.” Table 9-2. Signal Properties Function Oscillator or clock input Oscillator output System clock output Clock mode select inputs Reset signal from reset controller STPMD LOCKS LOCK TO RESET MODULE LOCS VCO RFD[2:0] SCALED PLL CLOCK OUT PLL CLOCK OUT Freescale Semiconductor ...
Page 175
... IPSBAR Offset 0x0012_0000 0x0012_0002 CPU supervisor mode access only. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 9-3. Clock Module Memory Map Register Name Synthesizer Control Register (SYNCR) Synthesizer Status Register (SYNSR) Clock Module Section 29.4.1, “Reset Control ...
Page 176
... Note: In external clock mode, the LOLRE bit has no effect. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev MFD1 MFD0 LOCRE 0010_0001 R FWKUP — STPMD1 0000_0000 R/W R IPSBAR + 0x0012_0000 Table 9-4. SYNCR Field Descriptions Description RFD2 RFD1 RFD0 STPMD0 — — R/W R Freescale Semiconductor ...
Page 177
... To avoid surpassing the allowable system operating frequency, write to RFD[2:0] only when the LOCK bit is set. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Description (( The following table illustrates the system frequency multiplier of the reference ...
Page 178
... Operation During Stop Mode System PLL Clocks 00 Disabled Enabled 01 Disabled Enabled 10 Disabled Disabled 11 Disabled Disabled PLLREF LOCKS LOCK See note 2 R IPSBAR + 0x0012_0002 Figure 9-4. Synthesizer Status Register (SYNSR) . OSC CLKOUT Enabled Enabled Enabled Disabled Enabled Disabled Disabled Disabled LOCS — 000 Freescale Semiconductor ...
Page 179
... PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 1 PLL locked 0 PLL not locked MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 9-5. SYNSR Field Descriptions Description Table 9-6. Table 9-6 ...
Page 180
... Table 9-6. System Clock Modes Clock Mode External clock mode 1:1 PLL mode Normal PLL mode with external clock reference Normal PLL mode with crystal reference Table × 2(MFD + 2)/ sys ref sys ref sys ref 27-8). The values of CLKMOD[1:0] are 1 PLL Options RFD Freescale Semiconductor ...
Page 181
... For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor CAUTION NOTE ...
Page 182
... The reference clock comes from either the crystal oscillator or an external clock source. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 9-12 8-MHz CRYSTAL CONFIGURATIO MΩ 470 Ω EXTAL XTAL V SSSYN RS RF Figure 9-5. Crystal Oscillator Example Figure to see how these Freescale Semiconductor ...
Page 183
... Phase lock is inferred by the frequency relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 9-8. ...
Page 184
... Set Relaxed Lock Condition and Notify System of Lock Condition Figure 9-6. Lock Detect Sequence Figure 9-6 shows the sequence Reference Count ≠ Feedback Count Count Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = Same Count/Compare Sequence Freescale Semiconductor ...
Page 185
... External External clock 1 The LOC circuit monitors the reference and feedback inputs to the PFD. See MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Section 29.4.2, “Reset Status Register NOTE Table 9-9. Loss of Clock Summary Reference Failure Alternate Clock ...
Page 186
... C LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit until reference regained 0–> 0–> 1–> Block LOCS and LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit — — — Freescale Semiconductor ...
Page 187
... Off On 1 Lose lock NRM NRM NRM Off X X Lose lock, f.b. clock, reference clock MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor PLL PLL Action MODE During Stop Out Stop Regain NRM Lose reference Stuck clock or no lock ...
Page 188
... REF mode not K 1 entered during stop — — — Wakeup without lock ‘LK 1 ‘ Wakeup without lock Wakeup without lock — — — ‘LC ‘LK 1 ‘ Wakeup without lock Wakeup without lock 0 0–> ‘LC 1 Freescale Semiconductor ...
Page 189
... X X SCM Off X 0 PLL disabled SCM Off X 1 PLL disabled SCM MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor PLL PLL Action MODE During Stop Out Stop — — NRM Lose lock or clock RESET RESET RESET — ...
Page 190
... CLK is never expected to regain MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 9-20 PLL PLL Action MODE During Stop Out Stop — — SCM Lose reference SCM clock Comments Freescale Semiconductor ...
Page 191
... For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor 10-1 ...
Page 192
... Definition” for more information on the stack frame format). Determination.” Table 10-1, which orders the interrupt levels/priorities from highest Table 10-1. Interrupt Priority Scheme Interrupt Priority Supported Interrupt Level ICR[IL] ICR[IP — (Mid-point Sources #8–63 #7 (IRQ7) #8–63 Freescale Semiconductor ...
Page 193
... Interrupt Recognition The interrupt controller continuously examines the request sources and the interrupt mask register to determine if there are active requests. This is the recognition phase. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Interrupt Priority Supported Interrupt Level ...
Page 194
... The nomenclature <reg_name>H and <reg_name>L is used to reference these values. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 10-4 then vector_number = 65 then vector_number = 66 then vector_number = 72 then vector_number = 73 then vector_number = 126 Freescale Semiconductor ...
Page 195
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 10-3. The offsets listed start from the base address 1 L1IACK–L7IACK)" for more information Bits[23:16] Interrupt Pending Register High (IPRH), [63:32] Interrupt Pending Register Low (IPRL), [31:1] ...
Page 196
... Reserved SWIACK L1IACK L2IACK L3IACK L4IACK L5IACK L6IACK L7IACK Figure 10-1 and Figure 10-2, are each 32 bits in size, and provide a bit INT[63:48] 0000_0000_0000_0000 R INT[47:32] 0000_0000_0000_0000 R IPSBAR + 0xC00, 0xD00 Bits[15:8] Bits[7:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 16 0 Freescale Semiconductor ...
Page 197
... The IMRn can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 10-4. IPRHn Field Descriptions Description ...
Page 198
... Figure 10-4. Interrupt Mask Register Low (IMRLn) MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 10-8 INT_MASK[63:48] 1111_1111_1111_1111 R/W INT_MASK[47:32] 1111_1111_1111_1111 R/W IPSBAR + 0xC08, 0xD08 Table 10-6. IMRHn Field Descriptions Description INT_MASK[31:16] 1111_1111_1111_1111 R/W INT_MASK[16:1] 1111_1111_1111_1111 R/W IPSBAR + 0xC0C, 0xD0C MASKALL Freescale Semiconductor ...
Page 199
... INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is cleared by reset. MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 Freescale Semiconductor Table 10-7. IMRLn Field Descriptions Description NOTE ...
Page 200
... MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3 10-10 INTFRCH[63:48] 0000_0000_0000_0000 R/W INTFRCH[47:32] 0000_0000_0000_0000 R/W IPSBAR + 0xC10, 0xD10 Table 10-8. INTFRCHn Field Descriptions Description INTFRCL[31:16] 0000_0000_0000_0000 R/W INTFRCL[16:1] 0000_0000_0000_0000 R/W IPSBAR + 0xC14, 0xD14 Table 10-9. INTFRCLn Field Descriptions Description — Freescale Semiconductor ...