MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 344

IC MPU 512K 80MHZ 256-MAPBGA

MCF5282CVM80

Manufacturer Part Number
MCF5282CVM80
Description
IC MPU 512K 80MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5282CVM80

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
Ram Memory Size
64KB
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Digital Ic Case Style
MAPBGA
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Fast Ethernet Controller (FEC)
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The
transmit FIFO stores at least the first 64 bytes of the transmit frame, so they do not have to be retrieved
from system memory in case of a collision. This improves bus utilization and latency in case immediate
retransmission is necessary.
When all the frame data is transmitted, FCS (frame check sequence) or 32-bit cyclic redundancy check
(CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in
the transmit frame control word, a bad CRC is appended to the frame data regardless of the TC bit value.
Following the transmission of the CRC, the Ethernet controller writes the frame status information to the
MIB block. Transmit logic automatically pads short frames (if the TC bit in the transmit buffer descriptor
for the end of frame buffer is set).
Settings in the EIMR determine interrupts generated to the buffer (TXB) and frame (TFINT).
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If
the transmit frame length exceeds MAX_FL bytes, BABT interrupt is asserted. However, the entire frame
is transmitted (no truncation).
To pause transmission, set TCR[GTS] (graceful transmit stop). The FEC transmitter stops immediately if
transmission is not in progress; otherwise, it continues transmission until the current frame finishes or
terminates with a collision. After the transmitter has stopped, the GRA (graceful stop complete) interrupt
is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame.
17.5.7.1
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously
until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame, it
begins to DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the TxBD
for the next frame. It is possible that the FEC fetches from memory a BD that has already been processed
but not yet written back (it is read a second time with the R bit remains set). In this case, the data is fetched
and transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct
operation for large or small frames, one of the following must be true:
17-34
The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.
Every frame uses more than one TxBD and every TxBD but the last is written back immediately
after the data is fetched.
The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is
then (Tx FIFO Size ÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less
than three). The default Tx FIFO size is 192 bytes; this size is programmable.
Duplicate Frame Transmission
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor

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