MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 207

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

service routine, and if there are additional active interrupt sources, the current interrupt service routine
(ISR) passes control to the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR
register is also loaded as the software IACK is performed. If there are no active sources, the interrupt
controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also
cleared.
In addition to the IACK registers within each interrupt controller, there are global LnIACK registers. A
read from one of the global LnIACK registers returns the vector for the highest priority unmasked interrupt
within a level for all interrupt controllers. There is no global SWIACK register. However, reading the
SWIACK register from each interrupt controller returns the vector number of the highest priority
unmasked request within that controller.
10.4
The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1 has the
lowest priority. If both interrupt controllers have active interrupts at the same level and priority, then the
INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has a higher level or priority
than the highest INTC0 interrupt, then the INTC1 interrupt will be serviced first.
10.5
The System Control Module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used
explicitly for controlling the low-power stop mode. This register must explicitly be programmed by
software to enter low-power mode.
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal
to exit from the low-power stop mode. This special mode of operation works as follows:
Freescale Semiconductor
•
Bits
7–0
First, LPICR[6:4] is loaded with the mask level that will be specified while the core is in stop mode.
LPICR[7] must be set to enable this mode of operation.
Prioritization Between Interrupt Controllers
Low-Power Wakeup Operation
VECTOR Vector number. A read from the SWIACK register returns the vector number associated with the
Figure 10-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
Name
Address
Reset
Field
R/W
highest level, highest priority unmasked interrupt source. A read from one of the LnACK registers
returns the highest priority unmasked interrupt source within the level.
Table 10-15. SWIACK and L1IACK-L7IACK Field Descriptions
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
7
See
6
Table 10-2
and
0000_0000
4
VECTOR
Table 10-3
Description
R
3
for register offsets
Interrupt Controller Modules
0
10-17