MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 549

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Freescale Semiconductor
QPR[6:0]
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
Bit(s)
11–7
6–0
Divisor
f
SYS
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
4
4
6
8
Name
QPR
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 28-4. QACR0 Field Descriptions (continued)
QPR[6:0]
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
Reserved, should be cleared.
Prescaler clock divider. Selects the system clock divisor to generate the QADC clock
as
where:
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler
divisor is 2.
The prescaler should be selected so that the QADC clock rate is within the required
f
QCLK
Table 28-5. Prescaler f
1 ≤ QPR[6:0] ≤ 127.
Table 28-5
range. See
shows. The resulting QADC clock rate can be given as:
Divisor
f
100
102
104
106
SYS
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Chapter 33, “Electrical
SYS
QPR[6:0]
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
Divide-by Values
f
QCLK
Description
=
Characteristics”.
2(QPR[6:0] + 1)
Divisor
Queued Analog-to-Digital Converter (QADC)
f
f
SYS
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
SYS
QPR[6:0]
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
Divisor
f
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
SYS
28-11