MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 433

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.3.9
The UACRs control the input enable.
23.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs provide status for all potential interrupt sources. UISRn contents are masked by UIMRn. If
corresponding UISRn and UIMRn bits are set, internal interrupt output is asserted. If a UIMRn bit is
cleared, state of the corresponding UISRn bit has no effect on the output.
The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user
with interrupt status, while writing controls the mask bits.
Freescale Semiconductor
Field
Field
COS
CTS
7–5
3–1
7–1
IEC
4
0
0
IPSBAR
Offset:
Reset:
Reserved
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 μs occurred on the UCTSn input. UACRn can be programmed to generate
Reserved
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of UCTSn. If
UCTSn is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the UCTSn input is asserted.
1 The current state of the UCTSn input is deasserted.
Reserved, must be cleared.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the
W
R
an interrupt to the CPU when a change of state is detected.
UCTSn input (if UIMRn[COS] = 1).
UART Auxiliary Control Register (UACRn)
0x00_0210 (UACR0)
0x00_0250 (UACR1)
0x00_0290 (UACR2)
0
0
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 23-11. UART Auxiliary Control Registers (UACRn)
6
0
0
Table 23-8. UIPCRn Field Descriptions
Table 23-9. UACRn Field Descriptions
0
0
5
0
0
4
Description
Description
0
0
3
0
0
2
Access: User write-only
0
0
1
UART Modules
IEC
0
0
23-13