MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 545

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.6
This subsection describes the QADC registers.
28.6.1
The QADCMCR contains bits that control QADC debug and stop modes and determine the privilege level
required to access most registers.
Freescale Semiconductor
1
2
3
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
Access results in the module generating an access termination transfer error if not in test mode.
Read/writes have no effect and the access terminates with a transfer error exception.
Address
0x19_0014–
0x19_0200–
0x19_0280–
0x19_0300–
0x19_0380–
0x19_027e
0x19_037e
IPSBAR +
0x19_01fe
0x19_02fe
0x19_03fe
Reset
Reset
R/W:
Field
R/W:
Field
Offset
Register Descriptions
QADC Module Configuration Register (QADCMCR)
QSTOP
SUPV
R/W
15
7
Figure 28-3. QADC Module Configuration Register (QADCMCR)
R/W
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QDBG
14
6
Table 28-2. QADC Memory Map (continued)
Right Justified, Unsigned Result Register (RJURR)
Left Justified, Unsigned Result Register (LJURR)
Left Justified, Signed Result Register (LJSRR)
MSB
Conversion Command Word Table (CCW)
13
IPSBAR + 0x19_0000, 0x19_0001
Reserved
0000_0000
1000_0000
(3)
—
R
—
R
Queued Analog-to-Digital Converter (QADC)
LSB
Access
8
0
S/U
S/U
S/U
S/U
—
1
28-7