MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 372

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

General Purpose Timer Modules (GPTA and GPTB)
20.4.3
The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with
externally-timed or clocked events. A high signal on this pin clears the counter.
20.5
See
0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000.
20-4
Table 20-3
0x1A_000C
0x1A_000D
0x1A_000A
0x1A_000B
0x1A_000E
0x1A_000F
0x1A_0000
0x1A_0001
0x1A_0002
0x1A_0003
0x1A_0004
0x1A_0006
0x1A_0007
0x1A_0008
0x1A_0009
0x1A_0010
0x1A_0011
0x1A_0012
0x1A_0013
0x1A_0014
0x1A_0015
0x1A_0016
GPTA
Memory Map and Registers
SYNCn
IPSBAR Offset
Reading reserved or unimplemented locations returns zeroes. Writing to
reserved or unimplemented locations has no effect.
for a memory map of the two GPT modules. GPTA has a base address of IPSBAR +
0x1Bb_0011
0x1B_0007
0x1B_0000
0x1B_0001
0x1B_0002
0x1B_0003
0x1B_0004
0x1B_0006
0x1B_0008
0x1B_0009
0x1B_000a
0x1B_000b
0x1B_000c
0x1B_000d
0x1B_000e
0x1B_0010
0x1B_0012
0x1B_0013
0x1B_0014
0x1B_0015
0x1B_0016
0x1B_000f
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
GPTB
Table 20-3. GPT Modules Memory Map
GPT Output Compare 3 Mask Register (GPTOC3M)
GPT Output Compare 3 Data Register (GPTOC3D)
GPT Toggle-on-Overflow Register (GPTTOV)
GPT Compare Force Register (GPTCFORC)
GPT System Control Register 1 (GPTSCR1)
GPT System Control Register 2 (GPTSCR2)
GPT Channel 0 Register High (GPTC0H)
GPT Channel 1 Register High (GPTC1H)
GPT Channel 2 Register High (GPTC2H)
GPT Channel 3 Register High (GPTC3H)
GPT Channel 0 Register Low (GPTC0L)
GPT Channel 1 Register Low (GPTC1L)
GPT Channel 2 Register Low (GPTC2L)
GPT Interrupt Enable Register (GPTIE)
GPT IC/OC Select Register (GPTIOS)
GPT Control Register 1 (GPTCTL1)
GPT Control Register 2 (GPTCTL2)
GPT Counter Register (GPTCNT)
GPT Flag Register 1 (GPTFLG1)
GPT Flag Register 2 (GPTFLG2)
NOTE
Reserved
Reserved
Bits 7–0
(2)
2
Freescale Semiconductor
Access
—
—
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
1