MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 336

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Fast Ethernet Controller (FEC)
Software produces buffers by allocating/initializing memory and initializing buffer descriptors. Setting the
RxBD[E] or TxBD[R] bit produces the buffer. Software writing to TDAR or RDAR tells the FEC that a
buffer is placed in external memory for the transmit or receive data traffic, respectively. The hardware
reads the BDs and consumes the buffers after they have been produced. After the data DMA is complete
and the DMA engine writes the buffer descriptor status bits, hardware clears RxBD[E] or TxBD[R] to
signal the buffer has been consumed. Software may poll the BDs to detect when the buffers are consumed
or may rely on the buffer/frame interrupts. The driver may process these buffers, and they can return to the
free list.
The ECR[ETHER_EN] bit operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is cleared,
the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer
descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor
must be initialized by software before ECR[ETHER_EN] is set.
The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs
and ETDSR defines the starting address for transmit BDs. The wrap (W) bit defines the last buffer
descriptor in each ring. When W is set, the next descriptor in the ring is at the location pointed to by
ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on
a 32-bit boundary; however, it is recommended they are made 128-bit aligned.
17.5.1.1.1
Driver/DMA Operation with Transmit BDs
Typically, a transmit frame is divided between multiple buffers. An example is to have an application
payload in one buffer, TCP header in a second buffer, IP header in a third buffer, and Ethernet/IEEE 802.3
header in a fouth buffer. The Ethernet MAC does not prepend the Ethernet header (destination address,
source address, length/type field(s)), so the driver must provide this in one of the transmit buffers. The
Ethernet MAC can append the Ethernet CRC to the frame. TxBD[TC], which must be set by the driver,
determines whether the MAC or driver appends the CRC.
The driver (TxBD software producer) should set up Tx BDs so a complete transmit frame is given to the
hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer,
length, and control (W, L, TC, ABC) and then the TxBD[R] bit should be set in reverse order (third,
second, then first BD) to ensure that the complete frame is ready in memory before the DMA begins. If
the TxBDs are set up in order, the DMA controller could DMA the first BD before the second was made
available, potentially causing a transmit FIFO underrun.
In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to TDAR.
When this register is written to (data value is not significant) the FEC, RISC tells the DMA to read the next
transmit BD in the ring. After started, the RISC + DMA continues to read and interpret transmit BDs in
order and DMA the associated buffers until a transmit BD is encountered with the R bit cleared. At this
point, the FEC polls this BD one more time. If the R bit is cleared the second time, RISC stops the transmit
descriptor read process until software sets up another transmit frame and writes to TDAR.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit,
indicating that the hardware consumer is finished with the buffer.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
17-26
Freescale Semiconductor