MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 139

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Freescale Semiconductor
5. Once an appropriately-high interrupt request level arrives, the interrupt controller signals its
6. The low-power mode control logic senses the request signal and re-enables the appropriate
7. With the processor clocks enabled, the core processes the pending interrupt request.
Bits
6–4
3–0
7
presence, and the SIM responds by asserting the request to exit low-power mode.
clocks.
ENBSTOP
XLPM_IPL
Only fixed (external) interrupt can bring a device out of stop mode. To exit
from other low-power modes, such as doze or wait, either fixed or
programmable interrupts may be used; however, the module generating the
interrupt must be enabled in that particular low-power mode.
Name
Address
—
XLPM_IPL[2:0]
Reset
Field ENBSTOP
R/W
000
001
010
011
100
101
11x
Figure 7-1. Low-Power Interrupt Control Register (LPICR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop
Exit low-power mode interrupt priority level. This field defines the interrupt priority level
needed to exit the low-power mode.Refer to
Reserved, should be cleared.
1/0
mode is asserted, processor clocks can be disabled.
7
Table 7-2. LPICR Field Descriptions
6
0
Table 7-3. XLPM_IPL Settings
Interrupts Level Needed to Exit Low-Power Mode
Interrupt request levels [2-7] exit low-power mode
Interrupt request levels [3-7] exit low-power mode
Interrupt request levels [4-7] exit low-power mode
Interrupt request levels [5-7] exit low-power mode
Interrupt request levels [6-7] exit low-power mode
Interrupt request level [7] exits low-power mode
XLPM_IPL
Any interrupt request exits low-power mode
1/0
NOTE
IPSBAR + 0x012
0
4
R/W
Description
3
Table
7-3.
Undefined
—
0
Power Management
7-3