MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 213

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4.2.3 Edge Port Interrupt Enable Register (EPIER)
11.4.2.4 Edge Port Data Register (EPDR)
Freescale Semiconductor
Bit(s)
Bit(s)
7–1
7–1
0
0
Address
Address
Reset
Reset
Field
Field
Name
EPIEx
Name
R/W
R/W
EPDx
—
—
Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
EPIE7
EPD7
7
7
Figure 11-5. EPORT Port Data Register (EPDR)
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is
set, EPORT generates an interrupt request when:
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT
pin. Reset clears EPIE7-EPIE1.
1 Interrupt requests from corresponding EPORT pin enabled
0 Interrupt requests from corresponding EPORT pin disabled
Reserved, should be cleared.
Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of
the port is configured as an output, the bit stored for that pin is driven onto the pin.
Reading EDPR returns the data stored in the register. Reset sets EPD7-EPD1.
Reserved, should be cleared.
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes
• The corresponding pin level is low and the pin is configured for level-sensitive
set.
operation.
Table 11-5. EPIER Field Descriptions
Table 11-6. EPDR Field Descriptions
EPIE6
EPD6
6
6
EPIE5
EPD5
5
5
IPSBAR + 0x0013_0003
IPSBAR + 0x0013_0004
R/W
R/W
0000_0000
1111_1111
EPIE4
EPD4
4
4
Description
Description
EPIE3
EPD3
3
3
EPIE2
EPD2
2
2
EPIE1
EPD1
1
1
Edge Port Module (EPORT)
—
—
R
R
0
0
11-5