PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 97

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

8.5
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (=1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISE bit (=0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register
reads and writes the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with several peripheral
functions (Table 8-9).
FIGURE 8-8:
 2000 Microchip Technology Inc.
PORTE, TRISE and LATE Registers
Note 1:
Peripheral Out Select
Peripheral Data Out
Peripheral Data In
Peripheral Enable
RD PORTE
WR TRISE
WR LATE
or
WR PORTE
Data Bus
PORTE BLOCK DIAGRAM
I/O pins have diode protection to V
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Pin
TRIS Latch
Data
D
D
CK
RD TRISE
CK
Latch
RD LATE
Override
Q
Q
Q
Q
Advanced Information
Yes
Yes
Yes
No
No
No
No
No
TRIS OVERRIDE
DD
Peripheral
PSP
PSP
PSP
—
—
—
—
—
and V
Override
TRIS
SS
0
1
.
Q
EXAMPLE 8-5:
CLRF
CLRF
MOVLW
MOVWF
EN
D
PORTE
LATE
0x03
TRISE
Schmitt
Trigger
V
V
N
P
SS
DD
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
PIC18CXX8
DS30475A-page 97
I/O Pin
(1)