PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 138

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
REGISTER 15-2:
DS30475A-page 138
bit 7
bit 6
bit 5
bit 4
SSPCON1 REGISTER
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
bit 7
WCOL
R/W-0
2
2
2
2
transmission to be started
cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting
overflow. In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.)
"don’t care" in Transmit mode. (Must be cleared in software.)
pins
port pins
C mode:
C mode:
C Slave mode:
C Master mode
SSPOV
R/W-0
Advanced Information
SSPEN
R/W-0
R/W-0
CKP
SSPM3
R/W-0
2
C conditions were not valid for a
SSPM2
R/W-0
 2000 Microchip Technology Inc.
SSPM1
R/W-0
SSPM0
R/W-0
bit 0