PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 88

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
7.1.6
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2, and RB3/INT3 pins are edge triggered:
either rising if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit INTxIF is set. This interrupt
can be disabled by clearing the corresponding enable
bit INTxIE. Flag bit INTxIF must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2, and
INT3) can wake-up the processor from SLEEP, if bit
INTxIE was set prior to going into SLEEP. If the global
interrupt enable bit GIE is set, the processor will branch
to the interrupt vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits
INT1IP (INTCON3 register), INT3IP (INTCON3 regis-
ter), and INT2IP (INTCON2 register). There is no prior-
ity bit associated with INT0; it is always a high priority
interrupt source.
7.1.7
In 8-bit mode (which is the default), an overflow (FFh →
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh → 0000h) in the
EXAMPLE 7-1:
DS30475A-page 88
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INT INTERRUPTS
TMR0 INTERRUPT
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
Advanced Information
; W_TEMP is in Low Access bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit TMR0IE (INTCON register). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2 register). See
Section 10.0 for further details on the Timer0 module.
7.1.8
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON register). The interrupt can be enabled/
disabled by setting/clearing enable bit RBIE (INTCON
register). Interrupt priority for PORTB interrupt-
on-change is determined by the value contained in the
interrupt priority bit RBIP (INTCON2 register).
7.2
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR reg-
isters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved.
Example 7-1 saves and restores the WREG, STATUS
and BSR registers during an Interrupt Service Routine.
PORTB INTERRUPT-ON-CHANGE
Context Saving During Interrupts
 2000 Microchip Technology Inc.