PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 295

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PIC18C858-E/L

Manufacturer Part Number
PIC18C858-E/L
Description
IC MCU OTP 16KX16 CAN 84PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr

Specifications of PIC18C858-E/L

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
84-PLCC
For Use With
AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C858E/L

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18C858-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example 1:
Example 2:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
N
Z
REG
N
Z
WREG
REG
N
Z
WREG
REG
N
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N,Z
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
?
?
1110 1011
1
0
?
1101 0111
?
?
1110 1011
1101 0111
1
0
f
[0,1]
[0,1]
255
dest<n-1>,
dest<7>
REG
REG, 0, 0
RRNCF f [ ,d [,a] ]
00da
Process
Data
Q3
register f
ffff
Advanced Information
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ’f’
Set f
[label] SETF
0
a
FFh
None
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
1
1
SETF
Read
0110
Q2
=
=
f
[0,1]
PIC18CXX8
255
f
0x5A
0xFF
100a
Process
Data
f [,a]
Q3
DS30475A-page 295
REG
ffff
register ’f’
Write
Q4
ffff

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