PIC18C858-E/L Microchip Technology, PIC18C858-E/L Datasheet - Page 130

• Manufacturer Part Number: PIC18C858-E/L
• Description: IC MCU OTP 16KX16 CAN 84PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C858-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 84-PLCC
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCDVA18XL840 - ADAPTER DEVICE ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C858E/L

PIC18CXX8
14.4
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value, or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
can have one of the following actions:
• Driven high
• Driven low
• Toggle output (high to low or low to high)
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit CCP1IF (CCP2IF) is set.
14.4.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM
DS30475A-page 130
Note:
Special Event Trigger will:
Compare Mode
CCP PIN CONFIGURATION
RC2/CCP1
Pin
RC1/CCP2
Pin
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)
Set bit GO/DONE, which starts an A/D conversion (CCP2 only)
Output Enable
Output Enable
TRISC<2>
TRISC<1>
I/O pins have diode protection to V
Q
Q
R
R
S
S
Special Event Trigger
Special Event Trigger
CCP1M3:CCP1M0
Mode Select
CCP2M3:CCP2M0
Mode Select
Output
Output
Logic
Logic
Advanced Information
DD
and V
Set Flag bit CCP1IF
Set Flag bit CCP2IF
SS
.
match
Match
14.4.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
14.4.3
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP Interrupt is gen-
erated (if enabled).
14.4.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note:
T3CCP1
T3CCP2
TMR1H
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
T3CCP2
TMR1L
CCPR1H CCPR1L
CCPR2H CCPR2L
Comparator
Comparator
 2000 Microchip Technology Inc.
0
0
1
1
TMR3H
TMR3L